RTL8201E(L)
Datasheet
9.2.3. RMII Transmission Cycle Timing (RTL8201E(L)-VB Only)
Table 35. RMII Transmission Cycle Timing (RTL8201E(L)-VB Only)
Symbol
Description
Minimum Typical Maximum Unit
REF_CLK Frequency
REF_CLK Duty Cycle
T_ipsu_txd_rmii
T_iphd_txd_rmii
Frequency of Reference Clock
Duty Cycle of Reference Clock
TXD/TXEN Setup Time to REFCLK
TXD/TXEN Hold Time from REFCLK
-
35
4
50
-
-
65
-
MHz
%
-
ns
2
-
-
ns
T_ipsu_txd_rmii
T_iphd_txd_rmii
REFCLK
TXD
Valid Data
Figure 13. RMII Transmission Cycle Timing
9.2.4. RMII Reception Cycle Timing (RTL8201E(L)-VB Only)
Table 36. RMII Reception Cycle Timing (RTL8201E(L)-VB Only)
Symbol
Description
Minimum Typical Maximum Unit
T_ipsu_rxd_rmii
T_iphd_rxd_rmii
RXD/CRS_DV Setup Time to REFCLK
RXD/CRS_DV Hold Time from REFCLK
4
2
-
-
-
-
ns
ns
T_ipsu_rxd_rmii
T_iphd_rxd_rmii
REFCLK
RXD
Valid Data
Figure 14. RMII Reception Cycle Timing
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
31
Track ID: JATR-1076-21 Rev. 1.3
REALTEK [ Realtek Semiconductor Corp. ]
