RTL8201E(L)
Datasheet
9.2.2. MII Reception Cycle Timing
Table 34. MII Reception Cycle Timing
Symbol Description
Minimum Typical Maximum Unit
t1
t2
t3
t4
t5
t6
t7
t8
t9
RXCLK High Pulse Width
RXCLK Low Pulse Width
RXCLK Period
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
10Mbps
14
140
14
140
-
20
26
260
26
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
200
20
200
260
-
40
-
400
-
RXER, RXDV, RXD[0:3]
Setup to RXCLK Rising Edge
10
10
10
10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RXER, RXDV, RXD[0:3]
Hold After RXCLK Rising Edge
-
-
Receive Frame to CRS High
130
2000
240
1000
150
3200
120
1000
-
End of Receive Frame to CRS Low
Receive Frame to Sampled Edge of RXDV
-
-
-
-
End of Receive Frame to Sampled Edge of RXDV 100Mbps
10Mbps
-
-
Figure 11 and Figure 12 show an example of a packet transfer from PHY to MAC on the MII interface.
t
3
V
V
RXCLK
I H(min)
I L(max)
t
t
2
t
t
5
4
1
RXD[0:3]
RXDV
V
V
I H(min)
I L(max)
RXER
Figure 11. MII Reception Cycle Timing-1
RXCLK
t9
t8
RXDV
RXD[0:3]
t6
t7
CRS
TPRX+-
Figure 12. MII Reception Cycle Timing-2
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
30
Track ID: JATR-1076-21 Rev. 1.3
REALTEK [ Realtek Semiconductor Corp. ]
