RTL8201E(L)
Datasheet
9.1.4. PHY Reset Sequence
Figure 8. PHY Reset Sequence
Table 30. PHY Reset Sequence Operating Conditions
Symbol
Rt1
Description
Minimum
Maximum
10ms
3.3V Rise Time (PHYRST)
1.2V Delay Time
1ms
Rt2
300µs
1ms
9.1.5. Power Dissipation
Test Condition: The data was measured from an RTL8201EL Demo Board. The total current
consumption is defined as the system current consumption, including AVDD3.3, DVDD3.3, AVDD1.2,
and DVDD1.2V power consumption, as well as regulator loss.
Table 31. Power Dissipation
Symbol
PLDPS
PAnaOff
PPWD
Condition
Total Current Consumption
Link Down Power Saving Mode
Analog Off Mode
Power Down Mode
100Base Full Duplex
10Base-T Full Duplex
10Base-T Transmit
10Base-T Receive
10Base-T Idle
27mA
20mA
15mA
62mA
67mA
66mA
29mA
27mA
P100F
P10F
P10TX
P10RX
P10IDLE
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
27
Track ID: JATR-1076-21 Rev. 1.3
REALTEK [ Realtek Semiconductor Corp. ]
