RTL8201E(L)
Datasheet
9.2.6. SNI Reception Cycle Timing
Table 38. SNI Reception Cycle Timing
Symbol Description
Minimum
Typical
Maximum
Unit
ns
t1
t2
t3
t4
t5
t6
t7
t8
RXCLK High Pulse Width
36
36
80
40
40
-
-
-
-
RXCLK Low Pulse Width
-
ns
RXCLK Period
-
120
-
ns
RXD0 Setup to RXCLK Rising Edge
RXD0 Hold after RXCLK Rising Edge
Receive Frame to CRS High
End of Receive Frame to CRS Low
Decoder Acquisition Time
-
ns
-
-
-
ns
50
160
1800
ns
-
-
ns
-
600
ns
Figure 17 and Figure 18 show an example of a packet transfer from PHY to MAC on the SNI interface.
Note: SNI mode only runs at 10Mbps.
Figure 17. SNI Reception Cycle Timing-1
Figure 18. SNI Reception Cycle Timing-2
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
33
Track ID: JATR-1076-21 Rev. 1.3
REALTEK [ Realtek Semiconductor Corp. ]
