RTL8201E(L)
Datasheet
9.2.5. SNI Transmission Cycle Timing
Table 37. SNI Transmission Cycle Timing
Symbol Description
Minimum
Maximum
Unit
ns
t1
t2
t3
t4
t5
t8
TXCLK High Pulse Width
36
36
80
20
10
-
-
-
TXCLK Low Pulse Width
ns
TXCLK Period
120
-
ns
TXEN, TXD0 Setup to TXCLK Rising Edge
TXEN, TXD0 Hold after TXCLK Rising Edge
Transmit Latency
ns
-
ns
50
ns
Figure 15 and Figure 16 show an example of a packet transfer from MAC to PHY on the SNI interface.
Note: SNI mode only runs at 10Mbps.
Figure 15. SNI Transmission Cycle Timing-1
TXCLK
TXEN
TXD0
t
8
TPTX+-
Figure 16. SNI Transmission Cycle Timing-2
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
32
Track ID: JATR-1076-21 Rev. 1.3
REALTEK [ Realtek Semiconductor Corp. ]
