RTL8201E(L)
Datasheet
8.1.2. Serial Management
The MAC layer device can use the MDC/MDIO management interface to control a maximum of 4
RTL8201E(L) devices, configured with different PHY addresses (00b to 11b).
During a hardware reset, the logic levels of pins 34/24 and 35/25 are latched into the RTL8201E(L) to be
set as the PHY address for management communication via the serial interface. The read and write frame
structure for the management interface is illustrated in Figure 4 and Figure 5.
MDC
Z
0
1
1
0
A4 A3 A2
A1 A0 R4 R3 R2 R1 R0
REGAD[4:0]
0
D14
D15 D13 D12
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DATA
32 1s
MDIO
Preamble
ST
OP
PHYAD[4:0]
TA
Idle
MDIO is sourced by PHY. Clock data from PHY on rising edge of MDC
MDIO is sourced by MAC. Clock data into PHY on rising edge of MDC
Figure 4. Read Cycle
MDC
0
1
0
1
A4 A3 A2 A1 A0 R4 R3 R2 R1 R0
PHYAD[4:0] REGAD[4:0]
1
0
D14
D11
D8 D7 D6 D5
DATA
MDIO
D15
D13 D12
D10 D9
D4 D3 D2 D1 D0
32 1s
OP
Preamble
ST
TA
Idle
MDIO is sourced by MAC. Clock data into PHY on rising edge of MDC
Figure 5. Write Cycle
Table 23. Serial Management
Name
Description
Preamble
32 Contiguous Logical 1’s Sent by the MAC on MDIO Along With 32 Corresponding Cycles on MDC.
This provides synchronization for the PHY.
ST
Start of Frame.
Indicated by a 01 pattern.
OP
Operation Code.
Read: 10
Write: 01
PHYAD
REGAD
TA
PHY Address.
Up to 4 PHYs can be connected to one MAC. This 2-bit field selects which PHY the frame is directed to.
Register Address.
This is a 5-bit field that sets which of the 32 registers of the PHY this operation refers to.
Turnaround.
This is a 2-bit-time spacing between the register address and the data field of a frame to avoid contention
during a read transaction. For a read transaction, both the STA and the PHY remain in a high-impedance
state for the first bit time of the turnaround. The PHY drives a zero bit during the second bit time of the
turnaround of a read transaction.
DATA
IDLE
Data.
These are the 16 bits of data.
Idle Condition.
Not truly part of the management frame. This is a high impedance state. Electrically, the PHY’s pull-up
resistor will pull the MDIO line to a logical ‘1’.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
19
Track ID: JATR-1076-21 Rev. 1.3
REALTEK [ Realtek Semiconductor Corp. ]
