RTL8201E(L)
Datasheet
8.8. Media Interface
8.8.1. 100Base-TX Transmit and Receive Operation
100Base-TX Transmit
Transmit data in 4-bit nibbles (TXD[3:0]) clocked at 25MHz (TXC) is transformed into 5B symbol code
(4B/5B encoding). Scrambling, serializing, and conversion to 125MHz, and NRZ to NRZI then takes
place. After this process, the NRZI signal is passed to the MLT-3 encoder, then to the transmit line driver.
The transmitter will first assert TXEN. Before transmitting the data pattern, it will send a /J/K/ symbol
(Start-of-frame delimiter), the data symbol, and finally a /T/R/ symbol known as the End-Of-Frame
delimiter. For better EMI performance, the seed of the scrambler is based on the PHY address. In a
hub/switch environment, each RTL8201E(L) will have different scrambler seeds and so spread the output
of the MLT-3 signals.
100Base-TX Receive
The received signal is compensated by the adaptive equalizer to make up for signal loss due to cable
attenuation and Inter Symbol Interference (ISI). Baseline Wander Correction monitors the process and
dynamically applies corrections to the process of signal equalization. The Phase Locked Loop (PLL) then
recovers the timing information from the signals and from the receive clock. With this, the received signal
is sampled to form NRZI (Non-Return-to-Zero Inverted) data. The next steps are the NRZI to NRZ (Non-
Return-to-Zero) process, unscrambling of the data, serial to parallel and 5B to 4B conversion, and passing
of the 4B nibble to the MII interface.
8.8.2. 100Base-FX Fiber Transmit and Receive Operation
The RTL8201E(L) can be configured to 100Base-FX mode via hardware configuration. The hardware
100Base-FX setting takes priority over NWay settings. A scrambler is not required in 100Base-FX.
100Base-FX Transmit
Di-bits of TXD are processed as 100Base-TX except without a scrambler before the NRZI stage. Instead
of converting to MLT-3 signals, as in 100Base-TX, the serial data stream is driven out as NRZI PECL
signals, which enter the fiber transceiver in differential-pair form.
100Base-FX Receive
The signal is received through PECL receiver inputs from the fiber transceiver and directly passed to the
clock recovery circuit for data/clock recovery. The scrambler/de-scrambler is bypassed in 100Base-FX.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
23
Track ID: JATR-1076-21 Rev. 1.3
REALTEK [ Realtek Semiconductor Corp. ]
