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RTL8201E-VB-GR 参数 Datasheet PDF下载

RTL8201E-VB-GR图片预览
型号: RTL8201E-VB-GR
PDF下载: 下载PDF文件 查看货源
内容描述: [Ethernet Transceiver, CMOS, PQCC32, GREEN, MO-220, QFN-32]
分类和应用: 以太网:16GBASE-T电信电信集成电路
文件页数/大小: 44 页 / 796 K
品牌: REALTEK [ Realtek Semiconductor Corp. ]
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RTL8201E(L)  
Datasheet  
Address Name  
Description  
Mode Default  
17:7  
17:6  
17:5  
17:4  
F_Link_100  
Used to logic force a good link in 100Mbps for diagnostic purposes.  
Set to 1 to enable jabber function in 10Base-T.  
Assertion of this bit causes a code error detection to be reported.  
RW  
RW  
RW  
RW  
1
1
0
0
JBEN  
CODE_err  
PME_err  
Assertion of this bit causes a pre-mature end error detection to be  
reported.  
17:3  
17:2  
LINK_err  
PKT_err  
Assertion of this bit causes a link error detection to be reported.  
RW  
RW  
0
0
Assertion of this bit causes a ‘detection of packet errors due to 722 ms  
time-out’ to be reported.  
17:1  
17:0  
FXMODE  
SNIMODE  
This bit indicates whether Fiber Mode is enabled.  
This bit indicates whether SNI Mode is enabled.  
RW  
RW  
0
0
7.10. Register 18 RX_ER Counter (REC)  
Table 20. Register 18 RX_ER Counter (REC)  
Address Name  
Description  
Mode  
Default  
18:15~0 RXERCNT  
This 16-bit counter increments by 1 for each invalid packet received.  
The value is valid while the link is established.  
RO  
0000  
7.11. Register 19 SNR Display Register  
Table 21. Register 19 SNR Display Register  
Address  
Name  
Description  
Mode  
Default  
19:15~4 Reserved  
Realtek Test Mode Internal Use.  
-
-
Do not change this field without Realtek’s approval.  
19:3~0  
SNR_0  
These 4-Bits Show the Signal to Noise Ratio Value.  
RW  
0000  
7.12. Register 25 Test Register  
Table 22. Register 25 Test Register  
Address Name  
Description  
Mode  
RW  
Default  
25:15~12 Test  
Reserved for Internal Testing.  
-
This Bit Decides the Type of TXC in RMII mode  
RW  
1
25:11  
25:10  
RMII_CLKIN  
0: Output  
1: Input  
RMII Mode  
This Bit Sets the RMII Mode.  
RW  
0
1: RMII mode  
Reserved.  
0: MII mode  
25:9  
Reserved  
-
-
25:7~8  
PHYAD[1:0]  
Reflects the PHY address defined by external PHY address  
configuration pins.  
RO  
00001  
25:6~2  
25:1  
Test  
Reserved for Internal Testing.  
RO  
RO  
-
LINK10  
1: 10Base-T link established  
0
0: No 10Base-T link established  
25:0  
LINK100  
1: 100Base-FX or 100Base-TX link established  
0: No 100Base link established  
RO  
0
Single-Chip/Port 10/100 Fast Ethernet PHYceiver  
with Auto MDIX  
16  
Track ID: JATR-1076-21 Rev. 1.3  
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