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RTL8201CL-VD 参数 Datasheet PDF下载

RTL8201CL-VD图片预览
型号: RTL8201CL-VD
PDF下载: 下载PDF文件 查看货源
内容描述: [Ethernet Transceiver, 1-Trnsvr, CMOS, PQFP48,]
分类和应用: 以太网:16GBASE-T电信电信集成电路
文件页数/大小: 39 页 / 529 K
品牌: REALTEK [ Realtek Semiconductor Corp. ]
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RTL8201CL  
Datasheet  
1. General Description  
The RTL8201CL is a single-chip/single-port PHYceiver with an MII (Media Independent Interface)/SNI  
(Serial Network Interface). It implements all 10/100M Ethernet Physical-layer functions including the  
Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), Twisted Pair Physical Medium  
Dependent Sublayer (TP-PMD), 10Base-Tx Encoder/Decoder, and Twisted-Pair Media Access Unit  
(TPMAU).  
A PECL (Pseudo Emitter Coupled Logic) interface is supported to connect with an external 100Base-FX  
fiber optical transceiver. The chip utilizes an advanced CMOS process to meet low voltage and low  
power requirements. With on-chip DSP (Digital Signal Processing) technology, the chip provides  
excellent performance under all operating conditions.  
The RTL8201CL can be used for applications such as those for a Network Interface Adapter, MAU  
(Media Access Unit), CNR (Communication and Network Riser), ACR (Advanced Communication  
Riser), an Ethernet hub, and an Ethernet switch. In addition, it can be used in any embedded system with  
an Ethernet MAC that needs a UTP physical connection or Fiber PECL interface to an external  
100Base-FX optical transceiver module.  
2. Features  
The Realtek RTL8201CL is a Fast Ethernet PHYceiver with selectable MII or SNI interface to the MAC  
chip. It provides the following features:  
„ Supports repeater mode  
„ Pin-to-pin compatible with the RTL8201BL  
„ Adaptive Equalization  
„ Supports MII and 7-wire SNI (Serial Network  
Interface)  
„ Network status LEDs  
„ 10/100Mbps operation  
„ Full/half duplex operation  
„ Twisted pair or fiber mode output  
„ Auto-Negotiation  
„ Flow control support  
„ 25MHz crystal/oscillator as clock source  
„ IEEE 802.3/802.3u compliant  
„ Supports IEEE 802.3u clause 28; 1.8V  
operation with 3.3V IO signal tolerance  
„ Supports power down mode  
„ Low dual power supply, 1.8V and 3.3V; 1.8V  
„ Supports operation under Link Down Power  
is generated by an internal regulator  
Saving mode  
„ 0.18µm CMOS process  
„ 48-pin LQFP package  
„ Supports Base Line Wander (BLW)  
compensation  
Single-Chip/Port 10/100 Fast Ethernet PHYceiver  
1
Track ID: JATR-1076-21 Rev. 1.24  
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