RTL8201CL
Datasheet
Table of Contents
1. GENERAL DESCRIPTION................................................................................................................................................1
2. FEATURES...........................................................................................................................................................................1
3. BLOCK DIAGRAM.............................................................................................................................................................2
4. PIN ASSIGNMENTS ...........................................................................................................................................................3
4.1.
LEAD (PB)-FREE PACKAGE IDENTIFICATION ................................................................................................................3
5. PIN DESCRIPTIONS ..........................................................................................................................................................4
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
5.8.
MII INTERFACE ............................................................................................................................................................4
SNI (SERIAL NETWORK INTERFACE) 10MBPS ONLY ....................................................................................................5
CLOCK INTERFACE .......................................................................................................................................................5
10MBPS/100MBPS NETWORK INTERFACE....................................................................................................................6
DEVICE CONFIGURATION INTERFACE ...........................................................................................................................6
LED INTERFACE/PHYADDRESS CONFIGURATION .......................................................................................................6
POWER AND GROUND PINS ..........................................................................................................................................7
RESET AND OTHER PINS...............................................................................................................................................7
6. REGISTER DESCRIPTIONS ............................................................................................................................................8
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
6.9.
6.10.
6.11.
6.12.
REGISTER 0 BASIC MODE CONTROL REGISTER............................................................................................................8
REGISTER 1 BASIC MODE STATUS REGISTER ...............................................................................................................9
REGISTER 2 PHY IDENTIFIER REGISTER 1....................................................................................................................9
REGISTER 3 PHY IDENTIFIER REGISTER 2....................................................................................................................9
REGISTER 4 AUTO-NEGOTIATION ADVERTISEMENT REGISTER (ANAR) ....................................................................10
REGISTER 5 AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER (ANLPAR)......................................................10
REGISTER 6 AUTO-NEGOTIATION EXPANSION REGISTER (ANER) .............................................................................11
REGISTER 16 NWAY SETUP REGISTER (NSR).............................................................................................................12
REGISTER 17 LOOPBACK, BYPASS, RECEIVER ERROR MASK REGISTER (LBREMR).................................................12
REGISTER 18 RX_ER COUNTER (REC) .....................................................................................................................13
REGISTER 19 SNR DISPLAY REGISTER.......................................................................................................................13
REGISTER 25 TEST REGISTER.....................................................................................................................................13
7. FUNCTIONAL DESCRIPTION.......................................................................................................................................14
7.1.
7.1.1.
7.1.2.
7.2.
7.2.1.
7.2.2.
7.2.3.
7.2.4.
MII AND MANAGEMENT INTERFACE ..........................................................................................................................14
Data Transition.....................................................................................................................................................14
Serial Management...............................................................................................................................................15
AUTO-NEGOTIATION AND PARALLEL DETECTION ......................................................................................................16
Setting the Medium Type and Interface Mode to MAC.........................................................................................16
UTP Mode and MII Interface ...............................................................................................................................16
UTP Mode and SNI Interface ...............................................................................................................................17
Fiber Mode and MII Interface..............................................................................................................................17
FLOW CONTROL SUPPORT ..........................................................................................................................................17
HARDWARE CONFIGURATION AND AUTO-NEGOTIATION ............................................................................................18
LED AND PHYADDRESS CONFIGURATION ................................................................................................................19
SERIAL NETWORK INTERFACE....................................................................................................................................20
POWER DOWN, LINK DOWN, POWER SAVING, AND ISOLATION MODES ......................................................................20
MEDIA INTERFACE .....................................................................................................................................................20
100Base-TX ..........................................................................................................................................................20
100Base-FX Fiber Mode Operation.....................................................................................................................21
10Base-T TX/RX ...................................................................................................................................................21
REPEATER MODE OPERATION.....................................................................................................................................22
RESET, AND TRANSMIT BIAS ......................................................................................................................................22
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.8.1.
7.8.2.
7.8.3.
7.9.
7.10.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
iv
Track ID: JATR-1076-21 Rev. 1.24
REALTEK [ Realtek Semiconductor Corp. ]
