RTL8201CL
Datasheet
REVISION HISTORY
Revision
Release Date
Summary
1.0
1.1
2003/06/09
2003/09/26
First release.
Minor cosmetic changes.
Modify LED Pin behavior.
1.2
2004/01/20
Add LED multi-mode definition (7.5 LED and PHY Address
Configuration, page 19).
Add Power dissipation info (Table 31).
Bit <0:8> default setting changed to 0 (Table 9).
Bit <0:13> default setting changed to 0 (Table 9).
Bit <5:7> default setting changed to 0 (Table 14).
Bit <17:5> default setting changed to 1 (Table 17).
Bit <25:0> default setting changed to 0 (Table 20).
Bit <25:1> default setting changed to 0 (Table 20).
Bit <25:11~7> default setting changed to 00001 (Table 20).
1.21
1.22
2004/10/12
2005/04/11
Package additions. See section 10, Ordering Information, page 33.
Correction to Table 18, Register 18 RX_ER Counter (REC), page 13.
Correction to Table 39, Transformer Characteristics, page 30.
Added lead (Pb)-free package identification information on page 3 and on
page 33.
1.23
2005/07/29
Corrected error in 7.8.3 10Base-T TX/RX, page 21 (10Base-T Transmit
Function _ clock at 25MHz => clock at 2.5MHz).
Corrections to Table 32, Input Voltage: Vcc, page 23.
Vcc _ TTL Voh _ Minimum 0.9*Vcc => Minimum 0.65*Vcc
Vcc _ TTL Vol _ Maximum 0.1*Vcc => Maximum 0.3*Vcc
Vcc _ TTL Ioz _ Minimum -10uA => Minimum -110uA
Vcc _ Iin _ Minimum -1.0uA => Minimum -110uA
Vcc _ Iin _ Maximum 1.0uA => Maximum 100uA
Revised Table 1, page 4 (pins 2, 3, 4, 5, 6, and 25).
Corrected Table 17, page 12 (bits 17:6 and 17:5).
Corrected Table 18, page 13 (mode).
1.24
2005/11/04
Revised Table 32, page 23 (IIN, IPL, IPH).
Revised Table 33, page 24 (t8).
Revised Table 34, page 25 (t6, t7, t9).
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
iii
Track ID: JATR-1076-21 Rev. 1.24
REALTEK [ Realtek Semiconductor Corp. ]
