RTL8201CL
Datasheet
3. Block Diagram
100M
5B 4B
Decoder
Data
Alignment
RXD
RXC 25M
Descrambler
MII
Interface
10/100
half/full
Switch
Logic
TXD
TXC 25M
4B 5B
Encoder
Scrambler
SNI
Interface
10/100M Auto-negotiation
Control Logic
Link pulse
10M
TXC10
TXD10
Manchester coded
waveform
10M Output waveform
shaping
RXC10
RXD10
Data Recovery
Receive low pass filter
TD+
TXC 25M
TXD
3 Level
Driver
TXO+
TXO -
Parrallel
to Serial
Variable Current
Baseline
wander
Correction
Peak
Detect
RXIN+
RXIN-
3 Level
Comparator
MLT-3
to NRZI
Adaptive
Equalizer
ck
RXC 25M
RXD
Serial to
Parrallel
Master
PPL
Slave
PLL
data
Control
Voltage
25M
Figure 1. Block Diagram
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
2
Track ID: JATR-1076-21 Rev. 1.24
REALTEK [ Realtek Semiconductor Corp. ]
