VRS51L1050
By default after reset, only the 256 bytes of SRAM
mapped to internal memory is accessible (access to
the remaining 768 bytes of SRAM is disabled). This
768 bytes can be enabled by setting the XRAME bit of
the SYSCON register located at address BFh in the
SFR.
Program Status Word Register
The PSW register is a bit-addressable register that
contains the status flags (CY, AC, OV, P), user flag
(F0) and register bank select bits (RS1, RS0) of the
8051 processor.
TABLE 12: PROGRAM STATUS WORD REGISTER (PSW) - SFR DOH
Lower 128 Bytes (00h to 7Fh, Bank 0 & Bank 1)
7
CY
6
AC
5
F0
4
RS1
3
RS0
2
OV
1
-
0
P
Details of the lower 128 bytes of data memory (from
00h to 7Fh) are summarized as follows:
Bit
Mnemonic Description
7
6
5
4
3
2
1
0
CY
AC
F0
RS1
RS0
OV
-
Carry bit
Auxiliary carry bit from bit 3 to 4.
User definer flag
R0-R7 Register bank select bit 0
R0-R7 Register bank select bit 1
Overflow flag
o
o
Address range 00h to 7Fh can be accessed in
direct and indirect addressing modes.
Address range 00h to 1Fh includes R0-R7
register areas.
Address range 20h to 2Fh is bit-addressable.
Address range 30h to 7Fh is not bit-
addressable and can be used as general
purpose storage.
o
o
-
P
Parity flag
RS1
RS0
Active Bank
Address
0
0
1
1
0
1
0
1
0
1
2
3
00h-07h
08h-0Fh
10h-17h
18-1Fh
Upper 128 Bytes (80h to FFh, Bank 2 & Bank 3)
The upper 128 bytes of data memory ranging from 80h
to FFh can be accessed using indirect addressing or
by using bank mapping in direct addressing mode.
Data Pointer
Stack Pointer
The VRS51L1050 has one 16-bit data pointer. The
DPTR is accessed via two SFR addresses: DPL
located at address 82h and DPH located at address
83h.
The stack pointer is a register located at address 81h
of the SFR register area whose value corresponds or
points to the address of the last item placed on the
processor stack. The stack pointer contents are
incremented each time new data is placed on the
stack.
Data Memory
The VRS51L1050 has 1KB of on-chip SRAM: 256
bytes are mapped into the internal memory bus as is
standard for 8052 MCUs. The remaining 768 bytes
(expanded SRAM) can be accessed using external
memory addressing via the MOVX instruction.
By default, the stack pointer value is 07h, but it is
possible to program the processor stack pointer to
point anywhere in the 00h to FFh range of SRAM.
When a function call is performed or an interrupt is
serviced, the 16-bit return address (two bytes) is stored
on the stack. Data can be placed manually on the
stack by using the PUSH and POP functions.
FIGURE 6: VRS51L1050 DATA MEMORY
02FF
Expanded SRAM Access Using the MOVX @DPTR
Instruction
Expanded 768 bytes
(accessed by direct
external addressing mode,
using the MOVX
The 768 bytes of expanded SRAM data memory
occupies addresses 0000h to 02FFh. This can be
accessed using external direct addressing (i.e. the
MOVX instruction). Note that in the case of indirect
addressing using the MOVX @DPTR instruction, if the
address is larger than 02FFh, the VRS51L1050 will
access off-chip memory in the external memory space
using the external memory control signals.
instruction)
(XRAME=1)
FF
Upper 128 bytes
SFR
(Indirect addressing mode only)
(Direct addressing mode Only)
80
7F
Lower 128 bytes
00
0000
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