VRS51C1000
Pulse Width Modulation (PWM)
TABLE 38: WATCHDOG TIMER REGISTER-SYSTEM CONTROL REGISTER (SYSCON)–SFR
BFH
7
6
5
4
3
2
1
0
ALEI
The Pulse Width Modulation (PWM) module consists
of five 8-bit channels. Each channel uses an 8-bit
PWM data register (PWMD) to set the number of
continuous pulses within a PWM frame cycle.
XRAME
WDR
Unused
IAPE
Bit
7
[6:3]
2
Mnemonic
WDR
Unused
IAPE
Description
Watchdog Timer Reset Bit
-
ISP Overall Enable Bit
1: Enables ISP Function
0: Disables ISP Function
PWM Function Description:
1
0
XRAME
ALEI
Each 8-bit PWM channel is composed of an 8-bit
register that consists of a 5-bit PWM (5 MSBs) and a
3-bit (LSBs) Narrow Pulse Generator (NP). The 5-bit
PWM determines the duty cycle of the output. The 3-bit
NPx generates and inserts narrow pulses among the
PWM frame made of 8 cycles.
1: Enable Electromagnetic Interference
Reducer
0: Disable Electromagnetic Interference
Reducer
As previously mentioned, bit 7 (WDR) of SYSCON is
the Watchdog Timer Reset bit. It will be set to 1 when
a reset signal is generated by the WDT overflow. The
user should check the WDR bit whenever an
unpredicted reset has taken place.
The number of pulses generated is equal to the
number programmed intp the 3-bit NP. The NP is used
to generate an equivalent 8-bit resolution PWM type
DAC with a reasonably high repetition rate through a 5-
bit PWM clock speed. The PDCK[1:0] settings of the
PWMC (A3h) register is used to derive the PWM clock
from Fosc.
Reduced EMI Function
The VRS51C1000 can also be set up for reduced EMI
(electromagnetic interference) by setting bit 0 (ALEI) of
the SYSCON register to 1. This function will inhibit the
Fosc/6Hz clock signal output to the ALE pin.
PWM Clock =
Fosc
2(PDCK [1:0] +1)
The PWM output cycle frame repetition rate
(frequency) is calculated using the following formula:
PWM Clock =
Fosc
32 x 2(PDCK [1:0] +1)
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