VRS51C1000
Watchdog Timer will generate a reset signal if an
overflow has taken place. The WDTE bit will be
cleared to 0 automatically when VRS51C1000 has
been reset by either the hardware or a WDT reset.
Clearing the WDT is accomplished by setting the CLR
bit of the WDTC to 1. This action will clear the contents
of the 16-bit counter and force it to restart.
Modifying the Order of Priority
The VRS51C1000 allows the user to modify the natural
priority of the interrupts. One may modify the order by
programming the bits in the IP (Interrupt Priority)
register. When any bit in this register is set to 1, it
gives the corresponding source a greater priority than
interrupts coming from sources that don’t have their
corresponding IP bit set to 1.
Watchdog Timer Registers
Two of the registers of the VRS51C1000 are
associated with the Watchdog Timer: WDTC and
SYSCON. The WDTC register allows the user to
enable the WDT, clear the counter and to divide the
clock source. The WDR bit of the SYSCON register
indicates whether the Watchdog Timer caused the
device reset.
The IP register is represented in the table below.
TABLE 35: IP INTERRUPT PRIORITY REGISTER –SFR B8H
7
EA
6
-
5
ET2
4
ES
3
ET1
2
EX1
1
ET0
0
EX0
Bit
Mnemonic Description
7
6
5
4
3
2
1
0
-
-
TABLE 36: WATCHDOG TIMER REGISTERS: WDTC – SFR 9FH
Gives Timer 2 Interrupt Higher Priority
PT2
PS
PT1
PX1
PT0
PX0
7
6
5
4
3
2
1
0
Gives Serial Port Interrupt Higher Priority
Gives Timer 1 Interrupt Higher Priority
Gives INT1 Interrupt Higher Priority
Gives Timer 0 Interrupt Higher Priority
Gives INT0 Interrupt Higher Priority
WDTE
Unused
CLR
Unused
PS2
PS1
PS0
Bit
7
6
5
[4:3]
2
1
Mnemonic
WDTE
Unused
CLR
Unused
PS2
Description
Watchdog Timer Enable Bit
-
Watchdog Timer Counter Clear Bit
-
Clock Source Divider Bit 2
Clock Source Divider Bit 1
Clock Source Divider Bit 0
PS1
PS0
Watchdog Timer
0
The Watchdog Timer (WDT) is a 16-bit free-running
counter that generates a reset signal if the counter
overflows. The WDT is useful for systems that are
susceptible to noise, power glitches and other
conditions that can cause the software to go into
infinite dead loops or runaways. The WDT function
gives the user software a recovery mechanism from
abnormal software conditions. The WDT is different
from Timer 0, Timer 1 and Timer 2 of the standard
8051.
Once the WDT is enabled, the user software must
clear it periodically. In the case where the WDT is not
cleared, its overflow will trigger a reset of the
VRS51C1000.
The user should check the WDR bit of the SYSCON
register whenever an unpredicted reset has taken
place.
The following table provides timeout periods
associated with different values of the PSx bits of the
Watchdog Timer Register.
TABLE 37: TIME PERIOD AT 40MHZ, 22.184MHZ AND 11.059MHZ
WDT
Period
40MHz
WDT
Period
22.18MHz
WDT
Period
12MHz
Divider
(OSC in)
PS [2:0]
000
001
010
011
100
101
110
111
8
16
13.11
26.21
23.63
47.27
43.69
87.38
32
52.43
94.53
174.76
349.53
699.05
1398.10
2796.20
5592.41
64
104.86
209.72
419.43
838.86
1677.72
189.07
378.14
756.28
1512.55
3025.10
128
256
512
1024
The WDT timeout delay can be adjusted by configuring
the clock divider input for the time base source clock of
the WDT. To select the divider value, bit2-bit0 (PS2-
PS0) of the Watchdog Timer Control Register (WDTC)
should be set accordingly.
To enable the WDT, the user must set bit 7 (WDTE) of
the WDTC register to 1. Once WDTE has been set to
1, the 16-bit counter will start to count with the selected
time base source clock configured in PS2~PS0. The
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