72Mbit Pipelined BSRAM
w/ NoBL Architecture
2Mx36
Preliminary Data Sheet
Capacitance (TA = 0°C to 70°C)
Symbol
CIN
Parameter
Min
2.5
3.5
Typical
Max
4
Units
pF
Notes
Input Capacitance
-
-
CI/O
Input/Output Capacitance
6
pF
AC Test Load
VH --
OUTPUT
90%
10%
tL
ALL
INPUTS
Z0 = 50Ω
RL = 50
Ω
-- VL
VTT
For VDD = 3.3V, AC timing tests use VL = 0V and VH = 3.0V. For VDDQ = 2.5V AC timing tests use VL = 0V and VH = 2.5V.
In both cases, input transit time tT must be ≤ 2 ns. Input timings are referenced to (VH-VL) / 2. Output timings are
referenced to VTT (for VDDQ = 3.3V, VTT = 1.5V and for VDDQ = 2.5V, VTT = 1.25V).
DC Equivalent Load
R1
VDDQ
For VDDQ = 2.5V
R1 = 422
R2 = 390
Ω
Ω
OUTPUT
CL = 5 pF
R2
For VDDQ = 3.3V
R1 = 317
R2 = 351
Ω
Ω
Including
Jig and
Scope
Package Thermal Characteristics
Symbol
θJA
Parameter
TQFP
PBGA
22
Units
°C/W
°C/W
Notes
1, 2, 3
2
Thermal Resistance (Junction to Ambient)
Thermal Resistance (Junction to Case)
25
10
8
θJC
Notes:
1. Tested in still air with device soldered to a 4.25 x 1.125 inch, 4-layer printed circuit board.
2. Tested initially and after any design or process changes that may affect these parameters.
3. Value accounts for thermal conduction through device leads or solder balls.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
Copyright 2001 Enhanced Memory Systems. All rights reserved.
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
The information contained herein is subject to change without notice.
Revision 1.0
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