72Mbit Pipelined BSRAM
w/ NoBL Architecture
2Mx36
Preliminary Data Sheet
Truth Table
Operation
Deselect
Address Used
CLK
CKE#
CE
F
LD#
L
R/W#
BWX#
Notes
1, 2
2
↑
↑
↑
↑
↑
↑
N/A
External
Next
L
L
L
L
L
H
X
H
X
L
X
X
X
V
V
X
Begin Read
Continue Read
Begin Write
Continue Write
Suspend
T
L
X
H
External
Next
T
L
2, 3
3
X
H
X
X
Current
X
X
4
Notes:
1. A deselect cycle is complete in four clocks.
2. T = True and F = False. CE is true when CE1# and CE3# are low and CE2 is high. CE is false when CE1# is high or CE2 is low or CE3# is
high.
3. V = Valid. During write cycles, the BWX# inputs must be valid (high or low) throughout the burst cycle.
4. If suspend occurs during a read, the DQ bus remains active (low-Z). During write and deselect cycles, the DQ bus remains in a high-Z state. No
write operations are performed during suspend.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
Copyright 2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.0
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RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
