72Mbit Pipelined BSRAM
w/ NoBL Architecture
2Mx36
Preliminary Data Sheet
-modify-write sequences, which are reduced to simple byte write operations. Because the SS2625 is a common I/O
device, data should not be driven into the device while the outputs are active. G# should be driven high before presenting
data to the DQ[a:d] inputs. This three-states the output drivers. As a safety precaution, DQ[a:d] are automatically three-stated
during the data portion of a write, regardless of the state of G#.
The SS2625 has an on-chip burst counter that increments on the rising edge of the clock when LD# is driven high. The
device then sequences through four address locations. If sequencing continues, this counter wraps around to the original
location. The appropriate BW[a:d]# inputs must be driven in each cycle to write the correct bytes of data.
The burst sequence is determined by the state of the LBO# input. See the Burst Order tables for the sequence. The LBO#
input signal is a strap pin and must remain static during device operation.
Deselecting the Device
Deselecting the SS2625 is accomplished by deasserting any of the chip enables while driving LD# low. The deselect
process requires four clock cycles to complete. When deselected the device enters a lower power state while still
monitoring the input signals to detect any new access. A deselect must occur at least once every 16 us (for example: once
every 1600 clock cycles at 100MHz). The DQ[a:d] pins are automatically three-stated two clocks after the deselection.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
Copyright 2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
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