64Mbit – Enhanced SDRAM
8Mx8, 4Mx16 ESDRAM
Preliminary Datasheet
Hidden Refresh (CL = 2, BL = 4)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
tRCD
tRP
tRC
tRC
tRC
tRAS
CS#
RAS#
CAS#
WE#
B0
C0
B0
R1
R1
R1
B0
B0
Bx
BA(1:0)
A11, A9
A10/AP
A(8:0)
DQM
Rx
Rx
Rx
C8
Q3
C12
Q10
Q0
Q1
Q2
Q8
Q9
Q11
Q12
Q13
Q14
Q15
DQ
Internal Status
Bank 0
Refresh
Active
Precharge
Refresh
R1
Active or Idle
Previously Loaded Row
Cache 0
This diagram shows three burst reads while the device performs two refresh cycles. Any of the four SRAM row caches
can be read while the DRAM is refreshing, precharging, or idle. All four banks must be idle before issuing an Auto-
Refresh (CBR) command.
This is a product in sampling or pre-production phase of development. Charac-
teristic data and other specifications are subject to change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
Revision 1.1
Page 27 of 33
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
