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SM2604T-6 参数 Datasheet PDF下载

SM2604T-6图片预览
型号: SM2604T-6
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM, 4MX16, 4.3ns, CMOS, PDSO54, TSOP-54]
分类和应用: 时钟动态存储器光电二极管
文件页数/大小: 33 页 / 305 K
品牌: RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
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Preliminary Datasheet
64Mbit – Enhanced SDRAM
8Mx8, 4Mx16 ESDRAM
Description
The SM2603 and 2604 Enhanced SDRAM (ESDRAM)
devices are JEDEC superset standard SDRAM. While
pin, function, and timing compatible with standard
SDRAM, they combine improved speed and innovative
architecture to optimize system price/performance in
high performance main memory, video graphics, and
embedded systems.
The four bank architecture combines 22.5 ns DRAM
arrays with 10.5 ns SRAM row caches. Three significant
functional features include early auto-precharge, hidden
RAS to CAS delay (t
RCD
), and an optional No Write
Transfer mode. The ESDRAM is capable of maintaining
four open read pages and four open write pages
simultaneously in No Write Transfer mode.
Features
High Performance 166 MHz Superset to SDRAM
100% Pin Compatible with SDRAM
100% Function and Timing Compatible with JEDEC
Standard SDRAM
Integrated 16 Kbit SRAM Row Cache
Low latency Operation
Synchronous Operation up to 166 MHz
2:2:2 @ 166 MHz
1:1:1 @ 83 MHz
Programmable Output Impedance (EMRS)
Programmable Burst Length (1, 2, 4, 8, full page)
Programmable CAS Latency (1, 2, 3)
Hidden Auto-Refresh Without Closing Read Pages
Low Power Suspend, Self Refresh, and Power Down
Modes Supported
Programmable Write Policy
Programmable Read DQM Latency = 1 for CL = 1
(EMRS)
4K Refresh / 64 ms
Single 3.3V Power Supply
Flexible V
DDQ
Supports LVTTL and 2.5V I/O
54-pin TSOP-II (0.8mm pin pitch)
Block Diagram (4Mx16 shown)
ADDRESS BUFFERS
ROW DECODER
BANK A
4K rows x
256 col x
16 bits
BANK B
4K rows x
256 col x
16 bits
BANK C
4K rows x
256 col x
16 bits
BANK D
4K rows x
256 col x
16 bits
BA1
BA0
A(11:0)
DATA LATCHES
DATA LATCHES
DATA LATCHES
SRAM ROW
CACHE
COLUMN
DECODER
SRAM ROW
CACHE
COLUMN
DECODER
SRAM ROW
CACHE
COLUMN
DECODER
SRAM ROW
CACHE
COLUMN
DECODER
CLK
CKE
CS#
RAS#
CAS#
WE#
UDQM
LDQM
Data I/O Buffers
COMMAND
DECODER
and
TIMING
GENERATOR
DQ(15:0)
This is a product in sampling or pre-production phase of development. Charac-
teristic data and other specifications are subject to change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095;
http://www.edram.com
Revision 1.1
Page 1 of 33
DATA LATCHES
SENSE
AMPLIFIERS
SENSE
AMPLIFIERS
SENSE
AMPLIFIERS
SENSE
AMPLIFIERS