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SM2604T-6 参数 Datasheet PDF下载

SM2604T-6图片预览
型号: SM2604T-6
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM, 4MX16, 4.3ns, CMOS, PDSO54, TSOP-54]
分类和应用: 时钟动态存储器光电二极管
文件页数/大小: 33 页 / 305 K
品牌: RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
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64Mbit – Enhanced SDRAM  
8Mx8, 4Mx16 ESDRAM  
Preliminary Datasheet  
Burst Length and Burst Type  
Bursting provides a constant flow of data to memory locations (writes), or from memory locations (reads). Burst length  
and burst type are programmable through address bits A0-A3 during a Mode Register Set command.  
Burst length defines the number of bits transferred after a Read or Write command. This value is programmable to one,  
two, four, eight, or full page (actual page length is dependent on device organization: x8 or x16). Full page bursting is  
only available with sequential type bursts. A burst does not automatically terminate in full page mode, but continues even  
after the page length is satisfied.  
Burst type defines the order in which the data is transferred. Both sequential and interleaved bursting is supported. For  
details see the table below.  
Burst Length and Type  
Burst Length  
2
Starting Address (A2 A1 A0)  
Sequential Addressing (decimal)  
0, 1  
Interleaved Addressing (decimal)  
0, 1  
xx0  
xx1  
x00  
x01  
x10  
x11  
000  
001  
010  
011  
100  
101  
110  
111  
nnn  
1, 0  
0, 1, 2, 3  
1, 2, 3, 0  
2, 3, 0, 1  
1, 0  
0, 1, 2, 3  
1, 0, 3, 2  
2, 3, 0, 1  
4
3, 0, 1, 2  
3, 2, 1, 0  
0, 1, 2, 3, 4, 5, 6, 7  
1, 2, 3, 4, 5, 6, 7, 0  
2, 3, 4, 5, 6, 7, 0, 1  
3, 4, 5, 6, 7, 0, 1, 2  
4, 5, 6, 7, 0, 1, 2, 3  
5, 6, 7, 0, 1, 2, 3, 4  
6, 7, 0, 1, 2, 3, 4, 5  
7, 0, 1, 2, 3, 4, 5, 6  
Cn, Cn+1, Cn+2, …  
0, 1, 2, 3, 4, 5, 6, 7  
1, 0, 3, 2, 5, 4, 7, 6  
2, 3, 0, 1, 6, 7, 4, 5  
3, 2, 1, 0, 7, 6, 5, 4  
4, 5, 6, 7, 0, 1, 2, 3  
5, 4, 7, 6, 1, 0, 3, 2  
6, 7, 4, 5, 2, 3, 0, 1  
7, 6, 5, 4, 3, 2, 1, 0  
Not Supported  
8
Full Page (Note)  
Note: Page length is a function of I/O organization and column addressing.  
x8 organization (CA0-CA8); Page Length = 512 column addresses  
x16 organization (CA0-CA7); Page Length = 256 column addresses  
This is a product in sampling or pre-production phase of development. Charac-  
teristic data and other specifications are subject to change without notice.  
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921  
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com  
Revision 1.1  
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