64Mbit – Enhanced SDRAM
8Mx8, 4Mx16 ESDRAM
Preliminary Datasheet
Performance Advantages
The ESDRAM delivers improved system performance by reducing latency and allowing concurrent operations to the
same bank in the DRAM array.
Reduced Latency
The ESDRAM core consists of high-speed (tRAC = 22.5ns) DRAM arrays. These fast arrays reduce the precharge time (tRP)
and the bank cycle time (tRC). Since reads always access the SRAM row cache, this allows the ESDRAM to perform
random column accesses at SRAM speeds.
Concurrent Operations and Row Pipelining
Using the SRAM row cache, the ESDRAM can also perform concurrent operations to the same bank. This ability
provides a significant increase in performance, in some cases effectively doubling memory bandwidth. The following is a
discussion of which concurrent operations are allowed and how system performance is maximized.
When a Bank Activate command is given, a row is selected and the sense amplifiers latch the data. Then a Read command
transfers the entire row into the SRAM row cache. Since all reads take data from the row cache, it is no longer necessary
to hold the DRAM bank open. By using a Read with Auto-Precharge command the DRAM array can be precharged on the
next clock cycle. Once the DRAM bank is precharged the system can issue an Auto-Refresh command or another Bank
Activate command during read accesses from the row cache.
The ability to perform a bank activate during a read gives a system the option of pipelined memory accesses to the same
bank. Using pipelining, the precharge time (tRP) and RAS to CAS delay (tRCD) of a page miss can be hidden during a burst
read. In the case of random row reads, pipelining can double memory bandwidth. Note that write bursts cannot be
pipelined because the DRAM bank must be held open, and therefore cannot be precharged, during Write command
execution.
Compatibility
By making the ESDRAM exactly pin compatible with JEDEC standard SDRAM, it is possible for the memory controller
to support both types of memory with a simple mode selection. Both SDRAM and ESDRAM use identical memory
footprints on the planar, and identical DIMM module wiring. Systems designed to support both memory types can provide
two distinct price/performance points and a simple field upgrade with the ESDRAM.
This is a product in sampling or pre-production phase of development. Charac-
teristic data and other specifications are subject to change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
