16Mbit ESDRAM Family
Architecture
The ESDRAM architecture combines two banks of fast
24ns DRAM with two banks of 11ns SRAM row register
cache on one chip to improve memory latency. On a page
read miss, a DRAM bank is activated and data is
developed by the DRAM sense amplifiers in 13.3ns. The
sense amplifiers now hold an entire row of data (4K bits).
On a read command, the entire row is latched into the
SRAM row register and the specified starting address is
output in 11ns (CAS Latency 1 at clock frequencies up to
83MHz, and CAS Latency 2 up to 150MHz). The
architecture allows fast 11ns latency to any of the
constantly open rows on page hits.
Early auto-precharge can be performed since row data is
latched separately in the SRAM row cache from the
DRAM sense amplifiers. The precharge time can be
hidden behind a burst read from cache. This minimizes
subsequent page miss latency. The auto-precharge begins
one clock cycle after the Read-Autoprecharge command
and completes early enough to allow the next pipelined
random access to complete by the end of the current burst
cycle.
At 150MHz, all but one cycle of the next random access
to any location in the same bank can be hidden to increase
sustained bandwidth by up to two times over standard
SDRAM. For interleaved burst read accesses, the entire
precharge time is hidden and output data can be driven
without any wait states.
The ESDRAM architecture also offers the designer two
different cache load strategies via the mode register set for
write cycles. In Write Transfer mode, the row register
cache is always loaded with the sense amplifier contents
(DRAM row data) on a write command. This ensures
coherency between the row cache and the DRAM array.
This allows read-modify-write cycles and simplified
memory control logic.
In No Write Transfer mode, the row register caches are
not loaded during writes. Data is written to the DRAM
sense amplifiers and the prior row contents are maintained
in the row cache (for write page misses). If the on-chip
page hit/miss comparator determines that the write is to
the same row latched in the SRAM row cache, the write
updates the row cache as well as the DRAM sense
amplifiers to maintain coherency. No Write Transfer
mode allows immediate return to the prior cached read
page without otherwise incurring a page miss penalty.
Write page precharge and a bank activate times can be
hidden during cache reads.
The ESDRAM’s fast
precharge time minimizes latency between the end of a
write and the next read or write miss cycle. If a cache
read follows a write cycle, write precharge time can be
hidden.
The synchronous interface of the ESDRAM allows
operation at clock rates up to 150MHz with 2.5V I/O
levels. Fast input set-up and clock-to-output times allow
actual system operation at the specified clock rate.
Compatibility
By making the ESDRAM exactly pin-compatible with
JEDEC standard SDRAM, it is possible for the memory
controller to support both types of memory with a simple
mode selection.
Both SDRAM and ESDRAM use
identical memory footprints on the planar and identical
DIMM module wiring. Systems designed to support both
memory types can provide two distinct price/performance
points and a simple field upgrade with the ESDRAM.
1Mx16
PINOUTS
4Mx4
2Mx8
VDD
DQ0
DQ1
VSSQ
DQ2
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
LDQM
/WE
/CAS
/RAS
/CS
A11 (BS)
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VSS
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS
VDD
NC
VSSQ
DQ0
VDDQ
NC
VSSQ
DQ1
VDDQ
NC
NC
/WE
/CAS
/RAS
/CS
VDD
DQ0
VSSQ
DQ1
VDDQ
DQ2
VSSQ
DQ3
VDDQ
NC
NC
/WE
/CAS
/RAS
/CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VSS
DQ7
VSSQ
DQ6
VDDQ
DQ5
VSSQ
DQ4
VDDQ
NC
NC
DQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS
VSS
NC
VSSQ
DQ3
VDDQ
NC
VSSQ
DQ2
VDDQ
NC
NC
DQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS
44 pin TSOP-II
400 x 725 mils
0.8 mm pitch
50 pin TSOP-II
400 x 825 mils
0.8 mm pitch
A11 (BS) A11 (BS)
A10/AP A10/AP
A0
A0
A1
A2
A3
VDD
A1
A2
A3
VDD
2
Rev. 2.4
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
