Internet Data Sheet
HY[B/I]25DC512[80/16]0D[E/F](L)
512-Mbit Double-Data-Rate SDRAM
TABLE 21
AC Operating Conditions
Parameter
Symbol
Values
Max.
Unit Note/ Test
Condition
Min.
1)2)3)
Input High (Logic 1) Voltage, DQ, DQS and DM Signals VIH.AC
Input Low (Logic 0) Voltage, DQ, DQS and DM Signals VIL.AC
V
REF + 0.31
—
V
1)2)3)
—
0.7
V
V
REF – 0.31
DDQ + 0.6
V
1)2)3)4)
Input Differential Voltage, CK and CK Inputs
Input Closing Point Voltage, CK and CK Inputs
VID.AC
VIX.AC
V
1)2)3)5)
0.5 × VDDQ– 0.2 0.5 × VDDQ+ 0.2
V
1) 0 °C ≤ TA ≤ 70 °C; VDD = VDDQ = 2.5 V ± 0.2 V, VDD = VDDQ = 2.6 V ± 0.1 V (DDR500)
2) Input slew rate = 1 V/ns.
3) Inputs are not recognized as valid until VREF stabilizes.
4) VID is the magnitude of the difference between the input level on CK and the input level on CK.
5) The value of VIX is expected to equal 0.5 × VDDQ of the transmitting device and must track variations in the DC level of the same.
TABLE 22
AC Timing - Absolute Specifications
Parameter
Symbol –4
DDR500B
–5/ –5A
–6
Unit Note/ Test
Condition 1)
DDR400A/B
DDR333B
Min.
Max.
Min.
Max. Min.
Max.
2)3)4)5)
DQ output access time from tAC
–0.7
+0.7
–0.7
+0.7
–0.7
+0.7
ns
CK/CK
2)3)4)5)
CK high-level width
Clock cycle time
tCH
tCK
0.45
0.55
12
0.45
5
0.55
12
8
0.45
0.55
12
tCK
4
4
5
6
6
6
ns
ns
ns
CL = 4.0 2)3)4)5)
CL = 3.0 2)3)4)5)
CL = 2.5 2)3)4)5)
12
5
12
12
6 for –5
12
12
5 for –5A
6
12
7
12
7.5
12
ns
CL = 2.0 2)3)4)5)
2)3)4)5)
CK low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
tCK
2)3)4)5)6)
Auto precharge write recovery tDAL
Min. : (tWR/tCK)+(tRP/tCK), Max. : —
+ precharge time
2)3)4)5)
DQ and DM input hold time
tDH
0.35
1.75
—
—
0.4
—
—
0.45
1.75
—
—
ns
ns
2)3)4)5)6)
DQ and DM input pulse width tDIPW
1.75
(each input)
2)3)4)5)
2)3)4)5)
DQS output access time from tDQSCK
CK/CK
–0.6
0.35
—
+0.6
—
–0.6
0.35
—
+0.6
—
–0.6
0.35
—
+0.6
—
ns
DQS input low (high) pulse
width (write cycle)
tDQSL,H
tDQSQ
tDQSQ
tCK
DQS-DQ skew (DQS and
associated DQ signals)
+0.35
+0.35
+0.40
+0.40
+0.45 ns
+0.40 ns
TSOPII
2)3)4)5)
DQS-DQ skew (DQS and
associated DQ signals)
—
—
—
TFBGA
2)3)4)5)
Rev. 1.10, 2008-05
27
06212007-08MW-K87L
QIMONDA [ QIMONDA AG ]
