Internet Data Sheet
HY[B/I]25DC512[80/16]0D[E/F](L)
512-Mbit Double-Data-Rate SDRAM
Parameter
Symbol –4
DDR500B
–5/ –5A
–6
Unit Note/ Test
Condition 1)
DDR400A/B
DDR333B
Min.
Max.
Min.
Max. Min.
Max.
2)3)4)5)
Read postamble
tRPST
0.40
8
0.60
—
0.40
10
0.60
—
0.40
12
0.60
—
tCK
2)3)4)5)
Active bank A to Active bank B tRRD
ns
command
2)3)4)5)
Write preamble
tWPRE
Max.
—
Max.
—
Max.
—
ns
(0.25 ×
(0.25 ×
(0.25 ×
t
CK, 1.5
t
CK, 1.5
tCK, 1.5
ns)
ns)
ns)
2)3)4)5)10)
Write preamble setup time
Write postamble
tWPRES
tWPST
tWR
0
—
0
—
0
—
ns
2)3)4)5)11)
0.40
15
2
0.60
—
0.40
15
2
0.60
—
0.40
15
1
0.60
—
tCK
2)3)4)5)
Write recovery time
ns
2)3)4)5)
Internal write to read
command delay
tWTR
—
—
—
tCK
2)3)4)5)
Exit self-refresh to non-read tXSNR
command
75
—
—
75
—
—
75
—
—
ns
2)3)4)5)
Exit self-refresh to read
command
tXSRD
200
200
200
tCK
1) 0 °C ≤ TA ≤ 70 °C; VDD = VDDQ = 2.5 V ± 0.2 V
2) Input slew rate ≥ 1 V/ns.
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time.
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
between VIH.AC and VIL.AC
.
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
10) The specific requirement is that DQS be valid (HIGH,LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specificationsof the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW at this time, depending
on tDQSS
.
11) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
Rev. 1.10, 2008-05
29
06212007-08MW-K87L
QIMONDA [ QIMONDA AG ]
