Internet Data Sheet
HY[B/I]25DC512[80/16]0D[E/F](L)
512-Mbit Double-Data-Rate SDRAM
TABLE 19
Input and Output Capacitances
Parameter
Symbol
Values
Unit Note/ Test Condition
Min. Typ. Max.
Input Capacitance: CK, CK
CI1
2.0
1.5
—
—
—
—
—
—
—
—
—
—
3.0
2.5
pF
pF
TSOPII1)
TFBGA 1)
1)
Delta Input Capacitance
CdI1
CI2
0.25 pF
Input Capacitance: All other input-only pins
1.5
2.0
—
2.5
3.0
0.5
4.5
5.0
0.5
pF
pF
pF
pF
pF
pF
TFBGA 1)
TSOPII 1)
1)
Delta Input Capacitance: All other input-only pins
Input/Output Capacitance: DQ, DQS, DM
CdIO
CIO
3.5
4.0
—
TFBGA 1)2)
TSOPII 1)2)
1)
Delta Input/Output Capacitance: DQ, DQS, DM
CdIO
1) These values are guaranteed by design and are tested on a sample base only. VDDQ = VDD = 2.5 V ± 0.2 V, f = 100 MHz, TA = 25 °C,
OUT(DC) = VDDQ/2, VOUT (Peak to Peak) 0.2 V. Unused pins are tied to ground.
V
2) DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at the
board level.
Rev. 1.10, 2008-05
24
06212007-08MW-K87L
QIMONDA [ QIMONDA AG ]
