Internet Data Sheet
HY[B/I]25DC512[80/16]0D[E/F](L)
512-Mbit Double-Data-Rate SDRAM
transfer and all other limitations apply (e.g. contention between READ data and WRITE data must be avoided). The minimum delay from
a read or write command with auto precharge enable, to a command to a different banks is summarized in Table 17.
10) A Write command may be applied after the completion of data output.
TABLE 17
Truth Table 6: Concurrent Auto Precharge
From Command
To Command (different bank)
Minimum Delay with Concurrent Auto Unit
Precharge Support
WRITE w/AP
Read or Read w/AP
Write to Write w/AP
Precharge or Activate
Read or Read w/AP
Write or Write w/AP
Precharge or Activate
1 + (BL/2) + tWTR
tCK
tCK
tCK
tCK
tCK
tCK
BL/2
1
Read w/AP
BL/2
CL (rounded up) + BL/2
1
Rev. 1.10, 2008-05
22
06212007-08MW-K87L
QIMONDA [ QIMONDA AG ]
