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HYB25DC512160DE-5A 参数 Datasheet PDF下载

HYB25DC512160DE-5A图片预览
型号: HYB25DC512160DE-5A
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 32MX16, 0.7ns, CMOS, PDSO66, GREEN, PLASTIC, TSOP2-66]
分类和应用: 时钟动态存储器双倍数据速率光电二极管内存集成电路
文件页数/大小: 38 页 / 2394 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HY[B/I]25DC512[80/16]0D[E/F](L)  
512-Mbit Double-Data-Rate SDRAM  
TABLE 16  
Truth Table 5: Current State Bank n - Command to Bank m (different bank)  
Current State CS RAS CAS WE Command  
Action  
Notes  
1)2)3)4)5)6)  
Any  
H
L
X
H
X
X
H
X
X
H
X
Deselect  
NOP. Continue previous operation  
1)2)3)4)5)6)  
1)2)3)4)5)6)  
No Operation  
NOP. Continue previous operation  
Idle  
X
Any Command  
Otherwise Allowed to  
Bank m  
1)2)3)4)5)6)  
Row  
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
H
L
Active  
Select and activate row  
Select column and start Read burst  
Select column and start Write burst  
1)2)3)4)5)6)7)  
1)2)3)4)5)6)7)  
1)2)3)4)5)6)  
Activating,  
Active, or  
Precharging  
H
H
L
Read  
L
Write  
H
H
L
L
Precharge  
Active  
1)2)3)4)5)6)  
Read (Auto  
Precharge  
Disabled)  
L
H
H
L
Select and activate row  
Select column and start new Read burst  
1)2)3)4)5)6)7)  
1)2)3)4)5)6)  
H
L
Read  
H
H
L
Precharge  
Active  
1)2)3)4)5)6)  
Write (Auto  
Precharge  
Disabled)  
L
H
H
L
Select and activate row  
Select column and start Read burst  
Select column and start new Write burst  
1)2)3)4)5)6)7)8)  
1)2)3)4)5)6)7)  
1)2)3)4)5)6)  
H
H
L
Read  
L
Write  
H
H
L
L
Precharge  
Active  
1)2)3)4)5)6)  
Read (With  
Auto  
Precharge)  
L
H
H
L
Select and activate row  
Select column and start new Read burst  
Select column and start Write burst  
1)2)3)4)5)6)7)9)  
1)2)3)4)5)6)7)9)10)  
1)2)3)4)5)6)  
H
H
L
Read  
L
Write  
H
H
L
L
Precharge  
Active  
1)2)3)4)5)6)  
Write (With  
Auto  
Precharge)  
L
H
H
L
Select and activate row  
Select column and start Read burst  
Select column and start new Write burst  
1)2)3)4)5)6)7)9)  
1)2)3)4)5)6)7)9)  
1)2)3)4)5)6)  
H
H
L
Read  
L
Write  
H
L
Precharge  
1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Table 14: Clock Enable (CKE) and after tXSNR/tXSRD has been met,  
if the previous state was self refresh)  
2) This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those  
allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in  
the notes below.  
3) Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated,  
and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A Read burst has been initiated, with  
Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge  
disabled, and has not yet terminated or been terminated.  
4) AUTO REFRESH and Mode Register Set commands may only be issued when all banks are idle.  
5) A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.  
6) All states and sequences not shown are illegal or reserved.  
7) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with  
Auto Precharge disabled.  
8) Requires appropriate DM masking.  
9) Concurrent Auto Precharge:This device supports “Concurrent Auto Precharge”. When a read with auto precharge or a write with auto  
precharge is enabled any command may follow to the other banks as long as that command does not interrupt the read or write data  
Rev. 1.10, 2008-05  
21  
06212007-08MW-K87L  
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