Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
4.3
Extended Mode Register 2 Set Command (EMRS2)
The Extended Mode Register 2 must be written after power
up to operate the GDDR3 Graphics RAM. The Extended
Mode Register 2 can be programmed by performing a normal
Mode Register Set operation and setting the BA1 bit to HIGH
and BA0, BA2 bits to LOW. All bits defined as RFU in the
bitmap are reserved and must be set to LOW. The Extended
Mode Register 2 must be loaded when all banks are idle and
no burst are in progress. The controller must wait the
specified time tMRD before initiating any subsequent
operation. The timing of the EMRS2 command operation is
equivalent to the timing of the MRS command operation.
FIGURE 13
Extended Mode Register 2 Set Command
CLK#
CLK
CKE
CS#
RAS#
CAS#
WE#
A0-A11
BA1
COD
1
0
COD: Code to be loaded into
the register
BA0,2
Don't Care
Rev. 0.92, 2007-10
06122007-MW7D-3G3M
25
QIMONDA [ QIMONDA AG ]
