Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
FIGURE 12
Timing of Vendor Code and Revision ID Generation on DQ[7:0]
0
1
2
3
4
5
6
7
8
9
10
CLK#
CLK
EMRS
Add
EMRS
Add
Com.
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
A[9:0],
A11
A10
t
t
RIDon
RIDoff
RDQS
DQ[7:0]
Vendor Code and Revision ID
EMRS: Extended Mode Register Set Command
Add:
N/D:
Address
NOP or Deselect
Don't Care
4.2.6
Address command termination
The address and command termination is used to set the value of the internal termination resistors. The GDDR3 DRAM
supports ZQ / 4, ZQ / 2 and ZQ termination values. The mode register programming overwrites the programming during the
chip initialization.
4.2.7
Operation mode
The GDDR3 DRAM can be internally configured as two 512Mbit (2-CS mode) or one 1Gbit device (1-CS mode). The pins CS1
and A12 are only active in two, resp. 1-CS mode and act either as the chip select for the second rank, or the row-address for
the upper 4k-row-address range. If bit A2 from EMRS2 (“Merged Mode”) is set to 1 then the 2 operations mode will be inverted.
Note also that at 1000 MHz speed grade only 1-CS mode is supported.
TABLE 10
Operation Mode Function of defined Merged Mode
Operation Mode
Merged Mode = 0
Merged Mode = 1
0
1
one-CS
two-CS
two-CS
one-CS
Rev. 0.92, 2007-10
24
06122007-MW7D-3G3M
QIMONDA [ QIMONDA AG ]
