Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
FIGURE 14
Extended Mode Register 2 Bitmap
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4.3.1
App Mode
The GDDR3 Graphics RAM provides two bitmaps for the Mode Register and the Extended Mode Register respectively. The
Bitmaps are shown in the MRS and EMRS chapters.
The Bit0 of the Extended Mode Regsiter 2 defines which one of the two bitmaps is active. There Bit0 set to LOW enables the
mid-range bitmap and Bit0 set to HIGH enables the High-Speed bitmap.
4.3.2
OCD Pull Down Offset
The 1G GDDR3 add the ability to add an offset to the Output impedance driver set using the bit A[1:0] of the EMRS. A range
from -3 to +3 can be chosen using A[11:9]. Each steps correspond to an approximate change of 1 Ohms. The offset will be
applied also on Autocal value if selected.
4.3.3
OCD Termination Pull Up Offset
The 1G GDDR3 add the ability to add an offset to the OCD Termination set using the bit A[3:2] of the EMRS. A range from -3
to +3 can be chosen using A[8:6]. Each steps correspond to an approximate change of 1.5 Ohms.
Rev. 0.92, 2007-10
26
06122007-MW7D-3G3M
QIMONDA [ QIMONDA AG ]
