Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
Parameter
Symbol
Limit Values
Unit Note
Min.
Typ.
Max.
1)
Reference Voltage
VREF
VOL(DC)
IIL
0.69*VDDQ
—
—
—
—
—
—
0.71*VDDQ
0.8
V
Output Low Voltage
Input leakage current
CLK Input leakage current
Output leakage current
V
2)
–5.0
+5.0
μΑ
IILC
–5.0
+5.0
μΑ
2)
IOL
–5.0
+5.0
μΑ
1)
VREF is expected to equal 70% of VDDQ for the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise
on VREF may not exceed ±2% VREF (DC). Thus, from 70% of VDDQ, VREF is allowed ± 19mV for DC error and an additional ± 27mV for AC
noise.
2)
I
IL and IOL are measured with ODT disabled.
5.3
DC & AC Logic Input Levels
TABLE 13
DC & AC Logic Input Levels (0 °C ≤ Tc ≤ 95 °C)
Parameter
Symbol
Min.
Limit Values
Unit Note
Max.
1)
Input logic high voltage, DC
Input logic low voltage, DC
Input logic high voltage, AC
Input logic low voltage, AC
Input logic high, DC, RESET pin
Input logic low, DC, RESET pin
Input Logic High, DC, MF pin
Input Logic Low,DC, MF pin
VIH(DC)
VIL(DC)
VIH(AC)
VIL(AC)
V
REF + 0.15
—
V
1)
—
VREF -0.15
V
2)3)
V
REF + 0.25
—
V
2)3)
—
V
REF - 0.25
DDQ + 0.3
V
V
V
V
V
IHR(DC)
ILR(DC)
IHMF(DC)
ILMF(DC)
0.65 × VDDQ
-0.3
V
V
V
0.35 × VDDQ
4)
VDD
VDD + 0.3
V
–0.3
0
V
1) The DC values define where the input slew rate requirements are imposed, and the input signal must not violate these levels in order to
maintain a valid level.
2) Input slew rate = 3 V/ns. If the input slew rate is less than 3 V/ns, input timing may be compromised. All slew rates are measured between
VIL(DC) and VIH(DC).
3)
V
IH overshoot: VIH(max) = VDDQ+0.5V for a pulse width ≤ 500ps and the pulse width cannot be greater than 1/3 of the cycle rate. VIL
undershoot: VIL(min) = 0 V for a pulse width ≤ 500ps and the pulse width cannot be greater than 1/3 of the cycle rate.
4) The MF pin must be hard-wired on board to either VDD or VSS
.
Rev. 0.92, 2007-10
29
06122007-MW7D-3G3M
QIMONDA [ QIMONDA AG ]
