Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
FIGURE 10
Extended Mode Register Bitmap for High-Speed Application
$ꢇ
$ꢆ
$ꢅ
$ꢄ
$ꢈ
$ꢃ
$ꢂ
$ꢀ
%$ꢃ %$ꢂ %$ꢀ $ꢂꢂ
$ꢂꢀ
9
$ꢁ
$ꢉ
ꢀ
ꢂ
5)8
&$ꢌ=
:5 '//
:5
5WW
'DWDꢌ=
0RGH
'//
(QDEOH
$''ꢊ&0'ꢌ
7HUPLQDWLRQ
2XWSXWꢌ'ULYHUꢌ
,PSHGDQFH
$ꢂꢀ 9HQGRUꢌ,'
$ꢆ
$ꢁ $ꢉ
$ꢂ $ꢀ
ꢀ
ꢂ
2II
2Q
(QDEOH
'LVDEOH
ꢀ
ꢂ
ꢀ
ꢀ
ꢂ
ꢂ
=4ꢌꢊꢌꢄ
=4ꢌꢊꢌꢃ
=4ꢌꢊꢌꢃ
=4
ꢀ
ꢂ
ꢀ
ꢂ
ꢀ
ꢀ
ꢂ
ꢂ
$XWRFDO
ꢈꢅꢌ2KPV
ꢄꢀꢌ2KPV
ꢄꢅꢌ2KPV
ꢀ
ꢂ
ꢀ
ꢂ
$ꢈ $ꢃ
7HUPLQDWLRQ
$ꢇ $ꢅ $ꢄ
:5
%$>ꢃ@
0RGH
ꢀ
ꢀ
ꢂ
ꢀ
ꢂ
ꢀ
2'7ꢌGLVDEOHG
5)8
ꢀ
ꢀ
ꢀ
ꢀ
ꢂ
ꢂ
ꢂ
ꢂ
ꢀ
ꢀ
ꢂ
ꢂ
ꢀ
ꢀ
ꢂ
ꢂ
ꢀ
ꢂ
ꢀ
ꢂ
ꢀ
ꢂ
ꢀ
ꢂ
ꢂꢂ
ꢂꢃ
ꢂꢈ
5)8
ꢇ
ꢀ
ꢂ
RQHꢏ&6
WZRꢏ&6
=4ꢌꢊꢌꢄ
ꢂ
ꢂ
=4ꢌꢊꢌꢃꢌꢍ'HIDXOWꢎꢌꢃꢎ
ꢉ
ꢁ
ꢂꢀ
([WHQGHGꢌ0RGHꢌ5HJLVWHUꢌIDVWꢋYVG
Notes
option implemented in the device) or no action is taken by
the device (if option not implemented).
5. WR (write recovery time for auto precharge) in clock
cycles is calculated by dividing tWR (in ns) and rounding up
to the next integer (WR[cycles] = tWR[ns] / tCK[ns]). The
mode register must be programmed to this value.
1. These settings are for debugging purposes only.
2. Default termination values at Power Up.
3. The ODT disable function disables all terminators on the
device.
4. If the user activates bits in the extended mode register in
an optional field, either the optional field is activated (if
FIGURE 11
Extended Mode Register Set Timing
CLK#
CLK
Command
PA
NOP
EMRS
NOP
NOP
A.C.
tRP
tMRD
A.C.: Any command
Don't Care
EMRS: Extended MRS command
PA: PREALL command
Rev. 0.92, 2007-10
22
06122007-MW7D-3G3M
QIMONDA [ QIMONDA AG ]
