HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
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Figure 3
Notes
Pin Configuration for ×16 components, PG-TFBGA-84-8
2. LDM is the data mask signal for DQ[7:0], UDM is the
data mask signal for DQ[15:8]
3. VDDL and VSSDL are power and ground for the DLL.
1. UDQS/UDQS is data strobe for DQ[15:8],
LDQS/LDQS is data strobe for DQ[7:0]
V
V
DDL is connected to VDD on the device. VDD, VDDQ
SSDL, VSS, and VSSQ are isolated on the device.
,
Internet Data Sheet
14
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
QIMONDA [ QIMONDA AG ]
