HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
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Figure 1
Notes
Pin Configuration for ×4 components, PG-TFBGA-60-24
2. Ball position L8 is A13 for 512-Mbit and is Not
Connected on 256-Mbit
1. VDDL and VSSDL are power and ground for the
DLL.They are isolated on the device from VDD
,
V
DDQ, VSS, and VSSQ
Internet Data Sheet
12
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
QIMONDA [ QIMONDA AG ]
