HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
Table 10
Field
BT
Mode Register Definition (BA[2:0] = 000B)
Bits Type1)
Description
Burst Type
3
w
0B
1B
BT, Sequential
BT, Interleaved
BL
[2:0]
w
Burst Length
Note:All other bit combinations are illegal.
010B BL, 4
011B BL, 8
1) w = write only register bits
2) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing tWR (in ns) by
tCK (in ns) and rounding up to the next integer: WR [cycles] ≥ tWR (ns) / tCK (ns). The mode register must be programmed to
fulfill the minimum requirement for the analogue tWR timing WRMIN is determined by tCK.MAX and WRMAX is determined by
tCK.MIN
.
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2TT
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!ꢉ
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!ꢄ
!ꢁ
2TT
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!ꢀ
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1
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ꢂ
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W
W
W
W
W
W
W
W
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Table 11
Field
Extended Mode Register Definition (BA[2:0] = 001B)
Bits Type1)
Description
reg. addr. Bank Address [2]
Note:BA2 not available on 256 Mbit and 512 Mbit components
0B BA2, Bank Address
Bank Address [1]
BA2
16
BA1
BA0
15
14
0B
BA1, Bank Address
Bank Address [0]
0B
BA0, Bank Address
Internet Data Sheet
17
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
QIMONDA [ QIMONDA AG ]
