HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
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Figure 2
Notes
Pin Configuration for ×8 components, PG-TFBGA-60-24
4. VDDL and VSSDL are power and ground for the DLL.
V
V
DDL is connected to VDD on the device. VDD, VDDQ
SSDL, VSS, and VSSQ are isolated on the device.
,
1. RDQS / RDQS are enabled by EMRS(1) command.
2. If RDQS / RDQS is enabled, the DM function is
disabled
3. When enabled, RDQS & RDQS are used as strobe
signals during reads.
5. Ball position L8 is A13 for 512-Mbit and is Not
Connected on 256-Mbit.
Internet Data Sheet
13
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
QIMONDA [ QIMONDA AG ]
