HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
Table 6
Pin Configuration of DDR2 SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
H8
H3
H7
J2
A0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Address Signal 12:0, Address Signal 10/Autoprecharge
A1
A2
A3
J8
A4
J3
A5
J7
A6
K2
K8
K3
H2
A7
A8
A9
A10
AP
A11
A12
A13
K7
L2
L8
Address Signal 13
Note: x4/x8 512 Mbit components
Note: and x16 512 Mbit components
NC
–
–
Address Signals ×16 organization
L2
BA0
BA1
NC
A0
I
I
–
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
–
Bank Address Bus 1:0
L3
L1
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Address Signal 12:0, Address Signal 10/Autoprecharge
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
P7
R2
Data Signals ×4 organizations
C8
C2
D7
D3
DQ0
DQ1
DQ2
DQ3
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
Data Signal 3:0
Internet Data Sheet
8
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
QIMONDA [ QIMONDA AG ]
