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HYB18TC1G800BF 参数 Datasheet PDF下载

HYB18TC1G800BF图片预览
型号: HYB18TC1G800BF
PDF下载: 下载PDF文件 查看货源
内容描述: 1千兆位双数据速率- SDRAM双 [1-Gbit Double-Data-Rate-Two SDRAM]
分类和应用: 动态存储器
文件页数/大小: 65 页 / 3555 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HYB18TC1G[80/16]0BF  
1-Gbit Double-Data-Rate-Two SDRAM  
TABLE 51  
DRAM Component Timing Parameter by Speed Grade - DDR2-400  
Parameter  
Symbol  
DDR2–400  
Unit  
Note1)2)3)4)5)  
6)  
Min.  
Max.  
DQ output access time from CK / CK  
CAS A to CAS B command period  
CK, CK high-level width  
tAC  
–600  
2
+600  
ps  
tCCD  
tCH  
tCKE  
tCL  
tCK  
tCK  
tCK  
tCK  
tCK  
0.45  
3
0.55  
CKE minimum high and low pulse width  
CK, CK low-level width  
0.45  
WR + tRP  
0.55  
7)20)  
8)  
Auto-Precharge write recovery + precharge  
time  
tDAL  
Minimum time clocks remain ON after CKE  
asynchronously drops LOW  
tDELAY  
tIS + tCK + tIH  
275  
––  
––  
ns  
ps  
ps  
9)  
DQ and DM input hold time (differential data  
strobe)  
tDH(base)  
10)  
DQ and DM input hold time (single ended data tDH1(base)  
–25  
strobe)  
DQ and DM input pulse width (each input)  
DQS output access time from CK / CK  
tDIPW  
0.35  
–500  
0.35  
tCK  
ps  
tCK  
ps  
tDQSCK  
+500  
DQS input low (high) pulse width (write cycle) tDQSL,H  
10)  
DQS-DQ skew (for DQS & associated DQ  
signals)  
tDQSQ  
350  
Write command to 1st DQS latching transition tDQSS  
– 0.25  
150  
+ 0.25  
tCK  
10)  
10)  
DQ and DM input setup time (differential data  
strobe)  
t
DS(base)  
ps  
DQ and DM input setup time (single ended  
data strobe)  
t
DS1(base)  
–25  
0.2  
ps  
DQS falling edge hold time from CK (write  
cycle)  
tDSH  
tCK  
DQS falling edge to CK setup time (write cycle) tDSS  
0.2  
tCK  
ns  
ns  
Four Activate Window period  
Four Activate Window period  
Clock half period  
tFAW  
tFAW  
tHP  
37.5  
12)  
11)  
12)  
10)  
50  
MIN. (tCL, tCH  
)
Data-out high-impedance time from CK / CK  
Address and control input hold time  
tHZ  
tAC.MAX  
ps  
ps  
tCK  
tIH(base)  
tIPW  
475  
0.6  
Address and control input pulse width  
(each input)  
10)  
13)  
13)  
Address and control input setup time  
DQ low-impedance time from CK / CK  
DQS low-impedance from CK / CK  
Mode register set command cycle time  
OCD drive mode output delay  
tIS(base)  
tLZ(DQ)  
tLZ(DQS)  
tMRD  
350  
ps  
ps  
ps  
tCK  
ns  
2 × tAC.MIN  
tAC.MAX  
tAC.MAX  
tAC.MIN  
2
0
tOIT  
12  
Data output hold time from DQS  
tQH  
t
HP tQHS  
Rev. 1.21, 2007-07  
50  
02282007-F8UP-4HSU  
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