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HYB18TC1G800BF 参数 Datasheet PDF下载

HYB18TC1G800BF图片预览
型号: HYB18TC1G800BF
PDF下载: 下载PDF文件 查看货源
内容描述: 1千兆位双数据速率- SDRAM双 [1-Gbit Double-Data-Rate-Two SDRAM]
分类和应用: 动态存储器
文件页数/大小: 65 页 / 3555 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HYB18TC1G[80/16]0BF  
1-Gbit Double-Data-Rate-Two SDRAM  
11) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can  
be greater than the minimum specification limits for tCL and tCH).  
12) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving  
(tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These  
parameters are verified by design and characterization, but not subject to production test.  
13) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C  
and 95 °C.  
14) 0 °CTCASE 85 °C  
15) 85 °C < TCASE 95 °C  
16) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.  
17) The tRRD timing parameter depends on the page size of the DRAM organization. See Table 5 “Ordering Information for RoHS compliant  
products” on Page 6.  
18) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system  
performance (bus turnaround) degrades accordingly.  
19) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.  
20) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-  
down mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow  
power-down exit timing tXARDS has to be satisfied.  
21) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded  
up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK  
refers to the application clock period. WR refers to the WR parameter stored in the MRS.  
Rev. 1.21, 2007-07  
52  
02282007-F8UP-4HSU  
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