W,+
ꢌ
W,6ꢌ
W,6ꢌ
ꢌ
ꢏꢌ
ꢏꢌ
9,ꢌ/ꢎGF ꢌPD[
ꢌ
ꢌ
ꢏꢌ
9,ꢌ/ꢎDF ꢌPD[
ꢏꢌ
W,+ꢌ
Internet Data Sheet
HYB18TC1G[80/16]0BF
1-Gbit Double-Data-Rate-Two SDRAM
FIGURE 9
Differential input waveform timing - tlS and tlH
&.ꢌ
&.ꢌ
9'ꢌ '4
9,ꢌ+ꢎDF ꢌPLQꢌ
9,ꢌ+ꢎGF ꢌPLQꢌ
95ꢌ ()ꢎGFꢏꢌ
96ꢌ 6ꢌ
TABLE 50
DRAM Component Timing Parameter by Speed Grade - DDR2–533
Parameter
Symbol
DDR2–533
Unit
Note1)2)3)4)5)
6)
Min.
Max.
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
tAC
–500
2
+500
—
ps
tCCD
tCH
tCKE
tCL
tCK
tCK
tCK
tCK
tCK
0.45
3
0.55
—
CKE minimum high and low pulse width
CK, CK low-level width
0.45
WR + tRP
0.55
—
7)17)
8)
Auto-Precharge write recovery + precharge
time
tDAL
Minimum time clocks remain ON after CKE
asynchronously drops LOW
tDELAY
tIS + tCK + tIH
225
––
––
—
ns
ps
ps
9)
DQ and DM input hold time (differential data
strobe)
tDH(base)
10)
DQ and DM input hold time (single ended data tDH1(base)
–25
strobe)
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
tDIPW
0.35
–450
0.35
—
—
tCK
ps
tCK
ps
tDQSCK
+450
—
DQS input low (high) pulse width (write cycle) tDQSL,H
10)
DQS-DQ skew (for DQS & associated DQ
signals)
tDQSQ
300
Write command to 1st DQS latching transition tDQSS
– 0.25
100
+ 0.25
—
tCK
10)
10)
DQ and DM input setup time (differential data
strobe)
t
DS(base)
ps
DQ and DM input setup time (single ended data tDS1(base)
–25
—
ps
strobe)
Rev. 1.21, 2007-07
47
02282007-F8UP-4HSU
QIMONDA [ QIMONDA AG ]
