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Internet Data Sheet
HYB18TC1G[80/16]0BF
1-Gbit Double-Data-Rate-Two SDRAM
30) For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which tRP = 15 ns, the device will support
tnRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
31) tWTR is at lease two clocks (2 x tCK) independent of operation frequency.
FIGURE 7
Method for calculating transitions and endpoint
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FIGURE 8
Differential input waveform timing - tDS and tDS
'46ꢌ
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Rev. 1.21, 2007-07
46
02282007-F8UP-4HSU
QIMONDA [ QIMONDA AG ]
