Internet Data Sheet
HYB18TC1G[80/16]0BF
1-Gbit Double-Data-Rate-Two SDRAM
30) For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which tRP = 15 ns, the device will support
tnRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
31) tWTR is at lease two clocks (2 x tCK) independent of operation frequency.
TABLE 49
DRAM Component Timing Parameter by Speed Grade - DDR2–667
Parameter
Symbol
DDR2–667
Unit
Note1)2)3)4)5)6)7)
Min.
Max.
8)
DQ output access time from CK / CK
CAS to CAS command delay
Average clock high pulse width
Average clock period
tAC
–450
2
+450
—
ps
tCCD
nCK
tCK.AVG
ps
9)10)
11)
tCH.AVG
tCK.AVG
0.48
3000
3
0.52
8000
—
CKE minimum pulse width ( high and low pulse tCKE
nCK
width)
9)10)
Average clock low pulse width
tCL.AVG
0.48
0.52
—
tCK.AVG
nCK
ns
12)13)
Auto-Precharge write recovery + precharge time tDAL
WR + tnRP
Minimum time clocks remain ON after CKE
asynchronously drops LOW
tDELAY
tIS + tCK .AVG
tIH
+
—
18)19)14)
8)
DQ and DM input hold time
tDH.BASE
tDIPW
tDQSCK
tDQSH
175
––
ps
DQ and DM input pulse width for each input
DQS output access time from CK / CK
DQS input high pulse width
0.35
–400
0.35
0.35
—
—
tCK.AVG
ps
+400
—
tCK.AVG
tCK.AVG
ps
DQS input low pulse width
tDQSL
—
15)
16)
DQS-DQ skew for DQS & associated DQ signals tDQSQ
240
+ 0.25
DQS latching rising transition to associated clock tDQSS
– 0.25
tCK.AVG
edges
17)18)19)
16)
DQ and DM input setup time
tDS.BASE
tDSH
tDSS
100
0.2
0.2
37.5
50
––
—
—
—
—
__
ps
DQS falling edge hold time from CK
DQS falling edge to CK setup time
tCK.AVG
tCK.AVG
ns
16)
30)
Four Activate Window for 1KB page size products tFAW
Four Activate Window for 2KB page size products tFAW
30)
ns
20)
CK half pulse width
tHP
Min(tCH.ABS
,
ps
tCL.ABS
)
8)21)
Data-out high-impedance time from CK / CK
Address and control input hold time
tHZ
—
tAC.MAX
—
ps
24)22)
tIH.BASE
275
0.6
ps
Control & address input pulse width for each input tIPW
—
tCK.AVG
ps
23)24)
8)21)
8)21)
30)
Address and control input setup time
DQ low impedance time from CK/CK
DQS/DQS low-impedance time from CK / CK
MRS command to ODT update delay
Mode register set command cycle time
tIS.BASE
200
—
tLZ.DQ
tLZ.DQS
tMOD
2 x tAC.MIN
tAC.MAX
tAC.MAX
12
ps
tAC.MIN
ps
0
2
ns
tMRD
—
nCK
Rev. 1.21, 2007-07
43
02282007-F8UP-4HSU
QIMONDA [ QIMONDA AG ]
