Internet Data Sheet
HYB18T512161BF–20/22/25/28/33
512-Mbit Double-Data-Rate-Two SDRAM
2
Pin Configuration
2.1
Pin Configuration
The pin configuration of a DDR2 SDRAM is listed by function in Table 2. The abbreviations used in the Pin#/Buffer Type
columns are explained in Table 3 and Table 4 respectively. The pin numbering for the FBGA package is depicted in Figure 1
for ×16.
TABLE 2
Pin Configuration of DDR SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
Clock Signals ×16 organization
J8
CK
I
I
I
SSTL
SSTL
SSTL
Clock Signal CK, Complementary Clock Signal CK
Clock Enable
K8
K2
CK
CKE
Control Signals ×16 organization
K7
L7
K3
L8
RAS
CAS
WE
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
CS
Chip Select
Address Signals ×16 organization
L2
L3
L1
BA0
BA1
NC
I
SSTL
SSTL
–
Bank Address Bus 1:0
I
–
Rev. 1.43, 2006-11
5
03292006-L40N-L04G
QIMONDA [ QIMONDA AG ]
