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Internet Data Sheet
HYB18T512161BF–20/22/25/28/33
512-Mbit Double-Data-Rate-Two SDRAM
TABLE 4
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminated Logic (SSTL_18)
Low Voltage CMOS
LV-CMOS
CMOS
OD
CMOS Levels
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
FIGURE 1
Pin Configuration for ×16 components, P-TFBGA-84 (top view)
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Note:
1. UDQS/UDQS is data strobe for DQ[15:8], LDQS/LDQS is
data strobe for DQ[7:0]
3. VDDL and VDDSL are power and ground for the DLL. They
are isolated on the device from VDD, VDDQ, VSS and VSSQ.
2. LDM is the data mask signal for DQ[7:0], UDM is the data
mask signal for DQ[15:8]
Rev. 1.43, 2006-11
8
03292006-L40N-L04G
QIMONDA [ QIMONDA AG ]
