Internet Data Sheet
HYB18T512161BF–20/22/25/28/33
512-Mbit Double-Data-Rate-Two SDRAM
HYB18T512161BF
Revision History: 2006-11, Rev. 1.43
Page
Subjects (major changes since last revision)
Adapted internet edtion
All
94-101
added chapter 7 explaining AC timing measurement condition (reference load ; slew rate ; set up & hold timing
references ; derating values for input /command ,data )
82-86
All
setup & hold timings are changed with reference to Industrial standard definition
removed all the occurances of RDQS as it in not used in graphics (x16)
Previous Revision: 2006-09, Rev. 1.32
All Qimonda Update
Previous Revision: 2006-03, Rev. 1.31
9
added power supply info for [-20 and -22]
86
table 41: change IDD max to IDD typ
77 - 80
Corrected AC Timing values for -20 speedsort in table 35 and table 36
Previous Revision: 2006-02, Rev. 1.21
67
71
76
77
78
86
table 18: added speed sort -20
table 24: added speed sort -20
table 33 and table 34: added speed sort -20
table 35: change CL=7 2.0 tCK (speed sort -20)
table 36: added all values for speed sort -20
table 41: added all IDD values (all speed sorts)
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-01
03292006-L40N-L04G
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