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HYB18T512161BF-20 参数 Datasheet PDF下载

HYB18T512161BF-20图片预览
型号: HYB18T512161BF-20
PDF下载: 下载PDF文件 查看货源
内容描述: 512 - Mbit的X16 DDR2 SDRAM [512-Mbit x16 DDR2 SDRAM]
分类和应用: 内存集成电路动态存储器双倍数据速率
文件页数/大小: 41 页 / 2261 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HYB18T512161BF–20/22/25/28/33  
512-Mbit Double-Data-Rate-Two SDRAM  
TABLE 30  
Timing Parameter by Speed Grade  
Parameter  
Symbol –28  
Min.  
–33  
Unit Note1)  
2)3)4)5)6)  
Max.  
Min.  
Max.  
DQ output access time from CK / CK  
CAS A to CAS B command period  
CK, CK high-level width  
tAC  
–550  
2
+550  
–600  
2
+600  
ps  
tCCD  
tCH  
tCKE  
tCL  
tCK  
tCK  
tCK  
tCK  
0.45  
3
0.55  
0.45  
3
0.55  
CKE minimum high and low pulse width  
CK, CK low-level width  
0.45  
WR + tRP  
0.55  
0.45  
WR + tRP  
0.55  
7)18)  
Auto-Precharge write recovery + precharge time tDAL  
tCK  
8)  
Minimum time clocks remain ON after CKE  
asynchronously drops LOW  
tDELAY  
tIS + tCK  
tIH  
+
––  
tIS + tCK  
tIH  
+
––  
ns  
9)  
DQ and DM input hold time (differential data  
strobe)  
tDH  
275  
25  
––  
––  
295  
45  
––  
––  
ps  
9)  
DQ and DM input hold time (single ended data tDH1  
ps  
strobe)  
DQ and DM input pulse width (each input)  
DQS output access time from CK / CK  
DQS input low (high) pulse width (write cycle)  
tDIPW  
0.35  
–550  
0.35  
0.35  
–600  
0.35  
tCK  
9)  
tDQSCK  
tDQSL,H  
tDQSQ  
+550  
+600  
ps  
tCK  
10)  
DQS-DQ skew (for DQS & associated DQ  
signals)  
450  
450  
ps  
Write command to 1st DQS latching transition  
tDQSS  
tDS  
WL – 0.25 WL + 0.25 WL – 0.25 WL + 0.25 tCK  
9)  
9)  
DQ and DM input setup time (differential data  
strobe)  
150  
––  
170  
––  
ps  
DQ and DM input setup time (single ended data tDS1  
25  
––  
45  
––  
ps  
strobe)  
DQS falling edge hold time from CK (write cycle) tDSH  
DQS falling edge to CK setup time (write cycle) tDSS  
0.2  
0.2  
0.2  
0.2  
tCK  
tCK  
11)  
12)  
Clock half period  
tHP  
tHZ  
tIH  
MIN. (tCL, tCH  
)
MIN. (tCL, tCH  
)
Data-out high-impedance time from CK / CK  
Address and control input hold time  
tAC.MAX  
tAC.MAX  
ps  
ps  
tCK  
625  
0.6  
675  
0.6  
Address and control input pulse width  
(each input)  
tIPW  
Address and control input setup time  
DQ low-impedance time from CK / CK  
tIS  
500  
550  
ps  
ps  
12)  
12)  
tLZ(DQ)  
2 ×  
tAC.MIN  
tAC.MAX  
2 ×  
tAC.MIN  
tAC.MAX  
DQS low-impedance from CK / CK  
Mode register set command cycle time  
OCD drive mode output delay  
Data output hold time from DQS  
Data hold skew factor  
tLZ(DQS)  
tMRD  
tOIT  
tAC.MIN  
tAC.MAX  
tAC.MIN  
tAC.MAX  
ps  
tCK  
ns  
ps  
µs  
µs  
2
0
2
0
12  
12  
tQH  
tHPtQHS  
t
HPtQHS  
tQHS  
tREFI  
600  
7.8  
3.9  
600  
7.8  
3.9  
13)14)  
13)15)  
Average periodic refresh Interval  
Rev. 1.43, 2006-11  
30  
03292006-L40N-L04G  
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