Internet Data Sheet
HYB18T512161BF–20/22/25/28/33
512-Mbit Double-Data-Rate-Two SDRAM
Parameter
Symbol –28
Min.
–33
Unit Note1)
2)3)4)5)6)
Max.
Min.
Max.
16)
Auto-Refresh to Active/Auto-Refresh command tRFC
105
—
105
—
ns
period
12)
Read preamble
Read postamble
tRPRE
tRPST
0.9
1.1
0.60
—
0.9
1.1
0.60
—
tCK
12)
0.40
10
0.40
10
tCK
14)17)
Active bank A to Active bank B command period tRRD
ns
Internal Read to Precharge command delay
Write preamble
tRTP
7.5
—
7.5
—
ns
tWPRE
tWPST
tWR
0.35 x tCK
0.40
15
—
0.35 x tCK
0.40
15
—
tCK
17)
Write postamble
0.60
—
0.60
—
tCK
Write recovery time for write without Auto-
Precharge
ns
18)
Write recovery time for write with Auto-Precharge WR
t
WR/tCK
—
—
—
t
WR/tCK
—
—
—
tCK
19)
Internal Write to Read command delay
tWTR
7.5
2
7.5
2
ns
20)
Exit power down to any valid command
(other than NOP or Deselect)
tXARD
tCK
20)
Exit active power-down mode to Read command tXARDS
(slow exit, lower power)
7 – AL
2
—
—
6 – AL
2
—
—
tCK
Exit precharge power-down to any valid
command (other than NOP or Deselect)
tXP
tCK
Exit Self-Refresh to non-Read command
tXSNR
tXSRD
t
RFC +10
—
—
t
RFC +10
—
—
ns
Exit Self-Refresh to Read command
200
200
tCK
1) VDDQ, VDD refer to Chapter 1.
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other Slew Rates see Chapter 5 of this
data sheet.
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross.The DQS / DQS input reference
level is the crosspoint when in differential strobe mode;The input reference level for signals other than CK/CK, DQS / DQS is defined in
Chapter 5.3 of this data sheet.
5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
6) The output timing reference voltage level is VTT. See Chapter 5 for the reference load for timing measurements.
7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to
the WR parameter stored in the MR.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock frequency change
during power-down, a specific procedure is required.
9) timing is referenced to Industrial standard definition
10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
mis-match between DQS / DQS and associated DQ in any given cycle.
11) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for tCL and tCH).
12) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
13) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
14) 0 °C ≤ TCASE ≤ 85 °C
15) 85 °C < TCASE ≤ 95 °C
16) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
Rev. 1.43, 2006-11
31
03292006-L40N-L04G
QIMONDA [ QIMONDA AG ]
