Internet Data Sheet
HYB18T512161BF–20/22/25/28/33
512-Mbit Double-Data-Rate-Two SDRAM
5.7.2
AC Timing Parameters
List of Timing Parameters
TABLE 29
Timing Parameter by Speed Grade
Parameter
Symbol –20
Min.
–22
–25
Unit Note1)
2)3)4)5)6)
Max. Min.
Max.
Min.
Max.
DQ output access time from CK /
CK
tAC
–450
+450 –450
+450
–500
+500
ps
CAS A to CAS B command period tCCD
CK, CK high-level width tCH
2
—
2
—
2
—
tCK
tCK
tCK
0.45
3
0.55
—
0.45
3
0.55
—
0.45
3
0.55
—
CKE minimum high and low pulse tCKE
width
CK, CK low-level width
tCL
0.45
0.55
—
0.45
0.55
—
0.45
0.55
—
tCK
7)18)
Auto-Precharge write recovery +
precharge time
tDAL
WR + tRP
WR + tRP
WR + tRP
tCK
8)
Minimum time clocks remain ON
after CKE asynchronously drops
LOW
tDELAY
tIS + tCK
tIH
+
––
tIS + tCK
tIH
+
––
tIS + tCK
tIH
+
––
ns
9)
DQ and DM input hold time
(differential data strobe)
tDH
145
-105
0.35
–450
0.35
—
––
––
—
220
-30
––
250
0
––
ps
9)
DQ and DM input hold time (single tDH1
ended data strobe)
––
––
ps
DQ and DM input pulse width (each tDIPW
input)
0.35
—
0.35
–500
0.35
—
—
tCK
9)
DQS output access time from CK / tDQSCK
CK
+450 –450
+450
—
+500
—
ps
DQS input low (high) pulse width
(write cycle)
tDQSL,H
tDQSQ
—
0.35
—
tCK
10)
DQS-DQ skew (for DQS &
associated DQ signals)
450
450
450
ps
Write command to 1st DQS latching tDQSS
transition
WL –
0.25
WL + WL –
WL +
0.25
WL –
0.25
WL +
0.25
tCK
0.25
0.25
9)
DQ and DM input setup time
(differential data strobe)
tDS
20
—
95
––
––
—
—
125
––
––
—
—
ps
9)
DQ and DM input setup time (single tDS1
ended data strobe)
-105
0.2
0.2
—
—
—
-30
0.2
0.2
0
ps
DQS falling edge hold time from CK tDSH
(write cycle)
0.2
0.2
tCK
tCK
DQS falling edge to CK setup time tDSS
(write cycle)
11)
Clock half period
tHP
MIN. (tCL, tCH
)
MIN. (tCL, tCH
)
MIN. (tCL, tCH
)
—
12)
Data-out high-impedance time from tHZ
—
tAC.MAX
—
tAC.MAX
—
tAC.MAX ps
CK / CK
Rev. 1.43, 2006-11
27
03292006-L40N-L04G
QIMONDA [ QIMONDA AG ]
