Internet Data Sheet
HYB18T512161BF–20/22/25/28/33
512-Mbit Double-Data-Rate-Two SDRAM
Parameter
Symbol –20
Min.
–22
–25
Unit Note1)
2)3)4)5)6)
Max. Min.
Max.
Min.
Max.
Address and control input hold time tIH
525
0.6
525
—
—
575
0.6
—
—
ps
Address and control input pulse
tIPW
—
—
0.6
tCK
width
(each input)
Address and control input setup
time
tIS
400
400
—
450
—
ps
12)
DQ low-impedance time from CK / tLZ(DQ)
CK
2 ×
tAC.MIN
tAC.MAX 2 ×
tAC.MIN
tAC.MAX tAC.MIN
tAC.MAX 2 ×
tAC.MIN
tAC.MAX tAC.MIN
tAC.MAX ps
tAC.MAX ps
12)
DQS low-impedance from CK / CK tLZ(DQS)
tAC.MIN
Mode register set command cycle tMRD
2
—
2
—
2
—
tCK
time
OCD drive mode output delay
Data output hold time from DQS
Data hold skew factor
tOIT
0
12
0
12
0
12
ns
—
ps
µs
µs
ns
tQH
t
HP–tQHS
—
t
HP–tQHS
—
t
HP–tQHS
—
tQHS
tREFI
—
600
7.8
3.9
—
—
—
—
105
600
7.8
3.9
—
—
—
—
105
600
7.8
3.9
—
13)14)
13)15)
16)
Average periodic refresh Interval
—
—
Auto-Refresh to Active/Auto-
Refresh command period
tRFC
105
12)
Read preamble
Read postamble
tRPRE
tRPST
tRRD
0.9
0.40
10
1.1
0.60
—
0.9
0.40
10
1.1
0.60
—
0.9
0.40
10
1.1
0.60
—
tCK
tCK
ns
12)
14)17)
Active bank A to Active bank B
command period
Internal Read to Precharge
command delay
tRTP
7.5
—
7.5
—
7.5
—
ns
Write preamble
Write postamble
tWPRE
tWPST
0.35 x tCK
0.40
—
0.35 x tCK
0.40
—
0.35 x tCK
0.40
—
tCK
tCK
ns
17)
0.60
—
0.60
—
0.60
—
Write recovery time for write without tWR
13
13
15
Auto-Precharge
18)
19)
20)
Write recovery time for write with
Auto-Precharge
WR
t
WR/tCK
—
—
—
t
WR/tCK
—
—
—
t
WR/tCK
—
—
—
tCK
ns
Internal Write to Read command
delay
tWTR
tXARD
7.5
2
7.5
2
7.5
2
Exit power down to any valid
command
tCK
(other than NOP or Deselect)
20)
Exit active power-down mode to
Read command (slow exit, lower
power)
tXARDS
10 – AL
2
—
—
9 – AL
2
—
—
8 – AL
2
—
—
tCK
Exit precharge power-down to any tXP
valid command (other than NOP or
Deselect)
tCK
Rev. 1.43, 2006-11
28
03292006-L40N-L04G
QIMONDA [ QIMONDA AG ]
